Two-step chemical-mechanical planarization for damascene structures on semiconductor wafers
AssigneeSpeedfam Corporation
InventorsThomas Laursen, Malcolm K. Grief, Krishna P. Murella, Sanjay Basak
Life of this patent
Estimating the term…
Abstract
A method of improving planarity of semiconductor wafer surfaces containing damascene and dual-damascene circuitry using chemical-mechanical polishing techniques. The method includes using a first polishing step to substantially remove excess surface metal up to a detected end point. After rinsing, a second step of chemical-mechanical polishing is applied, using a second slurry that has a higher selectivity for dielectric than metal, preferably from 1.8 to 4 or more times greater. The second step of polishing, in accordance with the invention, has been found to substantially eliminate dishing and improve planarity.
Claims3
A method of chemical-mechanical polishing of a surface of a semiconductor wafer containing metallic circuitry formed by a damascene or dual-damascene process, the method comprising:
- (i) polishing the wafer surface with a polishing pad and a first slurry the surface comprising a metallic layer overlying a conformal barrier layer, the barrier layer overlying dielectric, the metallic layer comprising plugs recessed into surrounding dielectric, the circuitry of the surface comprising a metal selected from the group consisting of copper, silver, gold, aluminum and alloys of these:
- (ii) detecting a first endpoint for polishing and preparing the wafer surface to receive a second slurry for a second step of polishing the first endpoint detected when the first metallic layer is substantially completely removed, the barrier layer is exposed on raised features of the wafer surface, and upper surfaces of the plugs are below the exposed barrier layer;
- and
- (iii) polishing the wafer surface with a second slurry having a rate of removal of from about 1.2 to about 4 times greater for dielectric than metal until a second endpoint is reached when the exposed barrier layer is removed and the upper surfaces of the plugs are flush with surrounding dielectric.
Dependencies are inferred from the claim text.