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US 6,555,460 B2Granted
Methods for mask repattern process
AssigneeMicron Technology, Inc.
InventorWarren M. Farnworth
Life of this patent
Estimating the term…
Abstract
The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.
Claims19
A method of forming portions of circuits connected to portions of integrated circuitry of a flip-chip semiconductor substrate, said method comprising:
- forming a semiconductor substrate having integrated circuitry, having at least one surface and having at least one circuit on a portion of said at least one surface of said semiconductor substrate connected to a portion of said integrated circuitry and terminating in a bond pad, said at least one circuit having a portion thereof covered by at least one first passivation layer while said bond pad remains substantially free of said at least one first passivation layer;
- forming a trace of solder wettable material from said bond pad of said at least one circuit to another location on said at least one surface of said semiconductor substrate, said trace of said solder wettable material contacting at least a portion of said bond pad of said at least one circuit and extending over a portion of said at least one first passivation layer, said trace of said solder wettable material having a first surface and a second surface, a portion of said second surface contacting said portion of said bond pad;
- forming at least one second passivation layer over said portion of said at least one surface of said semiconductor substrate and said trace of said solder wettable material;
- and
- etching a sloped-wall via through said at least one second passivation layer extending to a portion of said first surface of said trace of solder wettable material at said another location on said at least one surface of said semiconductor substrate.
2 more elements
A method of forming a metallization on a portion of a surface of a semiconductor substrate, said method comprising:
- forming a semiconductor substrate having integrated circuitry and having at least one surface, said semiconductor substrate including at least one solder wettable trace on at least a portion of said at least one surface connected to at least a portion of said integrated circuitry, said semiconductor substrate having at least one passivation layer over at least a portion of said at least one solder wettable trace on said at least a portion of said at least one surface;
- and
- forming a sloped-wall via in a portion of said at least one passivation layer to expose a portion of said at least one solder wettable trace.
A manufacturing method for an integrated circuit comprising:
- forming a substrate including integrated circuitry and at least one portion of a trace connected to said integrated circuitry, said at least one portion of said trace having one end thereof terminating in a bond pad;
- forming at least one first passivation layer over a portion of said at least one portion of said trace while said bond pad remains substantially free of said at least one passivation layer;
- forming another trace in contact with at least a portion of said bond pad of said at least one portion of said trace, a portion of said another trace extending over a portion of said at least one first passivation layer, said another trace having an upper surface;
- forming at least one second passivation layer over said portion of said another trace;
- forming a sloped-wall via through said at least one second passivation layer extending to a portion of said upper surface of said another trace;
- and
- forming a solder mass having a portion extending into said sloped-wall via contacting said portion of said upper surface of said another trace.
4 more elements
A manufacturing method for an integrated circuit comprising:
- forming a substrate including integrated circuitry having a portion thereof located on a portion of a surface of said substrate, another portion of said integrated circuitry terminating in at least one bond pad, at least one trace located on said portion of said surface of said substrate connected to said at least one bond pad of said integrated circuitry and having at least one passivation layer over at least said portion of said surface of the substrate;
- forming a sloped-wall via through a portion of said at least one passivation layer over said at least said portion of said surface of said substrate to expose one of at least a portion of said at least one trace and a portion of said at least one bond pad;
- and
- forming a solder mass having a portion extending into said sloped-wall via contacting one of said portion of said at least one trace and said portion of said at least one bond pad.
1 more element
Dependencies are inferred from the claim text.