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US 6,555,459 B1Granted
Method of manufacturing a semiconductor device
AssigneeSanyo Electric Co., Ltd.
InventorsRyoji Tokushige, Nobuyuki Takai, Hiroyuki Shinogi, Seiichi Ono
Life of this patent
Estimating the term…
Abstract
A metal post used with a chip size package and barrier metal formed on the metal post are omitted. After a second opening where a wiring layer is exposed is made, a second seed layer is formed and a solder post 7 is formed with the seed layer as a plate electrode.
Claims11
A method of manufacturing a semiconductor device comprising the steps of:
- providing a semiconductor wafer having a wiring layer made in contact with an electrode pad and consisting essentially of Cu extended on a chip surface, an insulating layer covering the chip surface containing the wiring layer, an opening made in the insulating layer on the wiring layer, and a seed layer formed on a surface containing an inner surface of the opening;
- forming solder in the opening by a plating method with the seed layer as a plate electrode;
- removing the seed layer surrounding the opening and allowing the seed layer and the solder to remain in the opening;
- and
- fixedly securing a solder ball on the solder remained.
2 more elements
Dependencies are inferred from the claim text.