Contact forming method for semiconductor device

A contact forming method for a semiconductor memory device having a cell array region and a peripheral circuit region comprising the steps of:

• forming a device isolation layer for defining an active region on a substrate of the cell array region and the peripheral circuit region;
• forming a gate deposition material on the device isolation layers of the peripheral circuit region, the active region of the peripheral circuit region, and the cell array region;
• forming sources/drains on the active region of the cell array region and the peripheral circuit region;
• forming a first insulating layer covering the gate deposition material on the substrate, and patterning the first insulating layer so that the sources/drains between the gate deposition material in the cell array region are exposed;
• filling regions where the sources/drains of the cell array region are exposed with conductive plugs;
• forming a second insulating layer on the first insulating layer, and forming contact holes by performing an etching process so that the conductive plugs of the cell array region, the sources/drains of the peripheral circuit region and the gate deposition material are exposed;
• forming a first conductive impurity layer on the exposed regions of the first insulating layer and conductive plugs;
• and
• forming a metal wiring layer in contact with the exposed regions of the conductive impurity layer.