Nonvolatile memory device and manufacturing method thereof
AssigneeVanguard International Semiconductor Corporation
InventorChao-Ming Koh
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Abstract
A nonvolatile memory device with a high coupling ratio is disclosed. The nonvolatile memory device includes a semiconductor substrate having shallow trench isolation (STI) formed therein and active regions defined. On the active regions, a floating gate is provided with a gate dielectric layer interposed. On the floating gate, a control gate is provided with a second dielectric layer interposed. The width of the floating gate is narrower than the active regions when viewed in transverse cross-section. A lighted doped region is optionally provided in the substrate at positions which are not covered by the floating gate. A manufacturing method for forming such memory device is also disclosed.
Claims9
A method for forming a nonvolatile memory device, comprising the steps of:
- forming a gate oxide layer on a silicon substrate;
- forming a first polysilicon layer on said gate oxide layer for serving as a floating gate of said memory device;
- patterning said first polysilicon layer, said gate oxide layer, and said substrate to form trenches in said substrate and to form a floating gate on an active region separated by said trenches with a patterned gate oxide layer interposed;
- thermally oxidizing surfaces of said first polysilicon layer and said trenches to form a liner oxide layer, thereby narrowing the width of said floating gate relative to said active region;
- forming isolation oxide in said trenches to form shallow trench isolation (STI);
- forming a lightly doped region in said substrate at positions which are not covered by said floating gate;
- and
- sequentially forming an interpoly oxide layer and a second polysilicon layer for serving as a control gate of said memory device over said substrate.
Dependencies are inferred from the claim text.