Method for forming integrated circuit capacitor and memory
AssigneeTexas Instruments Incorporated
InventorsGuoqiang Xing, Scott R. Summerfelt, Rajesh Khamankar
Life of this patent
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Abstract
A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer 824 between the platinum layer and the second material; forming a hardmask layer 829 over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer 832, the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti—Al—N including at least 1% of aluminum.
Claims7
A method for fabricating memory cell of a memory circuit, comprising the steps of:
- (a) forming a transistor at a substrate surface, said transistor comprising a wordline control terminal and first and second terminals;
- (b) forming a bitline contact to said first terminal;
- (c) covering said transistor with an interlayer dielectric;
- (d) removing a portion of said interlayerr dielectric to form a contact to said second transistor terminal;
- (e) forming a conductive plug in an opening formed by the removal of said portion of said interlayer dielectric, said conductive plug including a barrier portion;
- (f) covering said interlayer dielectric with an adhesion-promoting layer, said adhesion-promoting layer contacting said barrier portion;
- (g) covering said adhesion-promoting layer with an a bottom electrode layer;
- (h) covering said bottom electrode layer with a hardmask layer;
- (i) removing portions of said hardmask layer to form a bottom electrode pattern of said hardmask layer;
- (j) etching portions of said bottom electrode layer not covered by said bottom electrode pattern of said hardmask layer to form a bottom electrode, said adhesion-promoting layer inhibiting removal of said interlayer dielectric;
- (k) simultaneously removing portions of said adhesion-promoting layer not covered by said bottom electrode and of said bottom electrode pattern hardmask layer;
- (l) covering said bottom electrode with a storage material;
- and
- (m) covering said storage layer with a top electrode.
Dependencies are inferred from the claim text.