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US 6,555,394 B2Granted
Methods of fabricating capacitors including Ta2O5 layers in a chamber including changing a Ta2O5 layer to heater separation or chamber pressure
AssigneeSamsung Electronics Co., Ltd.
InventorsKi-yeon Park, Heung-soo Park, Young-wook Park
Life of this patent
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Abstract
Methods of forming Ta2O5 layers in a process chamber are disclosed. A Ta2O5 layer can be maintained at a first temperature that is less than a temperature for crystallization of the Ta2O5 layer. At least one of a position of the Ta2O5 layer in the process chamber relative to the heater and a pressure in the process chamber is changed to increase the temperature of the Ta2O5 layer to about the temperature for crystallization.
Claims15
A method of manufacturing a capacitor of a semiconductor device comprising the steps of:
- forming a lower electrode on a semiconductor substrate;
- forming a Ta2O5 layer on the lower electrode;
- curing the Ta2O5 layer by annealing the Ta2O5 layer in a process chamber in an ozone atmosphere at a temperature that is less than a crystallization temperature of the Ta2O5 layer;
- and then
- crystallizing the Ta2O5 layer by heating the Ta2O5 layer in the same process chamber to a temperature that is greater than or equal to the crystallization temperature of the Ta2O5 layer, wherein a heater maintains the Ta2O5 layer at a second temperature that is greater than or equal to the crystallization temperature of the Ta2O5 layer between curing the Ta2O5 layer and crystallizing the Ta2O5 layer;
- wherein a plurality of moveable pins control a separation distance between the semiconductor substrate and a stage on which the Ta2O5 layer is mounted by moving the plurality of pins up and down to move the stage relative to the heater;
- and
- the step of curing is performed in a first state where the plurality of pins are moved up to a predetermined height from the stage such that the semiconductor substrate is apart from the stage by a predetermined distance, and
- the step of crystallizing is performed in a second state where the plurality of pins are not projected from the stage so that the semiconductor substrate remains in contact with the stage.
6 more elements
Dependencies are inferred from the claim text.