Inter-functional-block restriction high-speed extraction method and recording medium having stored thereon an inter-functional-block restriction high-speed extraction program
AssigneeNEC Corporation
InventorsSawako Kataoka, Yasuteru Makita
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Abstract
In an algorithm for a logic synthesis procedure in which the gate conversion and optimization are conducted according to boundary conditions and optimizing conditions of input/output interfaces set for each unit, timing restriction of boundary sections can be obtained in a short period of time from an RTL description before the logic synthesis is executed. A boundary section is extracted from the RTL description before execution of logic synthesis. Using the boundary section, the logic synthesis and a design budget are executed to obtain timing restriction for the boundary section.
Claims14
An inter-functional-block restriction high-speed extraction method of converting, according to a top restriction describing boundary conditions and optimizing conditions of boundary sections between units for a logic circuit described at a register transfer level, the register-transfer-level logic circuit into a gate-level logic circuit and of optimizing the gate-level logic circuit, comprising the following steps of:
- extracting boundary sections from the logic circuit described at a register transfer level;
- conducting logic synthesis only for the boundary sections extracted;
- extracting a timing restriction according to a design of each of the boundary sections resultant from the logic synthesis;
- and
- conducting logic synthesis at a unit level when no timing violation is detected according to the timing restriction extracted and/or
- conducting logic synthesis at a unit level when a timing violation is detected according to the timing restriction extracted, the logic synthesis using the timing restriction as an input thereto;
- extracting a timing restriction according to a design of the boundary section resultant from the logic synthesis;
- and
- determining whether or not a timing violation is detected according to the timing restriction extracted.
An inter-functional-block restriction high-speed extraction method of converting, according to a top restriction describing boundary conditions and optimizing conditions of boundary sections between units for a logic circuit described at a register transfer level, the register-transfer-level logic circuit into a gate-level logic circuit and of optimizing the gate-level logic circuit, comprising the following steps of:
- extracting, using the register-transfer-level logic circuit as an input thereto, boundary sections from the register-transfer-level logic circuit;
- conducting, using the boundary sections extracted, first logic synthesis only for the boundary sections according to a unit initial restriction;
- executing, using a design resultant from the first logic synthesis, a first design budget according to the top restriction;
- executing, using a timing restriction resultant from the first design budget, second logic synthesis;
- executing, using a design resultant from the second logic synthesis, a second design budget according to the top restriction;
- determining, according to a timing restriction resultant from the second design budget, whether or not a timing violation is present;
- conducting logic synthesis at a unit level when no timing violation is present as a result of the determination and/or
- conducting, when a timing violation is present according to the timing restriction resultant from the second design budget, again the second logic synthesis using the timing restriction as an input thereto.
An inter-functional-block restriction high-speed extraction method of converting, according to a top restriction describing boundary conditions and optimizing conditions of boundary sections between units for a logic circuit described at a register transfer level, the register-transfer-level logic circuit into a gate-level logic circuit and of optimizing the gate-level logic circuit, the method consisting of a first and second process wherein;
- said first process comprising the following steps of:
- extracting, using the register-transfer-level logic circuit as an input thereto, boundary sections from the register-transfer-level logic circuit;
- conducting, using the boundary sections extracted, first logic synthesis only for the boundary sections according to a unit initial restriction;
- and
- executing, using a design resultant from the first logic synthesis, a first design budget according to the top restriction;
- said second process executing two times or more and comprising the following steps of:
- executing, using a timing restriction resultant from the first design budget, second logic synthesis;
- executing, using a design resultant from the second logic synthesis, a second design budget according to the top restriction;
- determining, according to timing restriction resultant from the second design budget, whether or not timing violation is present;
- conducting, when a timing violation is present according to the timing restriction resultant from the second design budget, again the second logic synthesis using the timing restriction as an input thereto.
A recording medium having stored thereon an inter-functional-program restriction high-speed extraction program to convert, according to a top restriction describing boundary conditions and optimizing conditions of boundary sections between units for a logic circuit described at a register transfer level, the register-transfer-level logic circuit into a gate-level logic circuit and to optimize the gate-level logic circuit, the program conducting:
- extracting boundary sections from the logic circuit described at a register transfer level;
- conducting logic synthesis only for the boundary sections extracted;
- extracting a timing restriction according to a design of each of the boundary sections resultant from the logic synthesis;
- and
- conducting logic synthesis at a unit level when no timing violation is detected according to the timing restriction extracted and/or:
- conducting, when a timing violation is detected according to the timing restriction extracted, again the logic synthesis using the timing restriction as an input thereto;
- extracting a timing restriction according to a design of the boundary section resultant from the logic synthesis;
- and
- determining whether or not a timing violation is detected according to the timing restriction extracted.
A recording medium having stored thereon an inter-functional-program restriction high-speed extraction program to convert, according to a top restriction describing boundary conditions and optimizing conditions of boundary sections between units for a logic circuit described at a register transfer level, the register-transfer-level logic circuit into a gate-level logic circuit and to optimize the gate-level logic circuit, the program conducting the following steps of:
- extracting, using the register-transfer-level logic circuit as an input thereto, boundary sections from the register-transfer-level logic circuit;
- conducting, using the boundary sections extracted, first logic synthesis only for the boundary sections according to unit initial restriction;
- executing, using a design resultant from the first logic synthesis, a first design budget according to a top restriction;
- executing, using a timing restriction resultant from the first design budget, second logic synthesis;
- executing, using a design resultant from the second logic synthesis, a second design budget according to the top restriction;
- determining, according to timing restriction resultant from the second design budget, whether or not a timing violation is present;
- and
- conducting logic synthesis at a unit level when no timing violation is present as a result of the determination and/or;
- conducting, when a timing violation is present according to a timing restriction resultant from the second design budget, again the second logic synthesis using a timing restriction as an input thereto.
A recording medium having stored thereon an inter-functional-program restriction high-speed extraction program to convert, according to a top restriction describing boundary conditions and optimizing conditions of boundary sections between units for a logic circuit described at a register transfer level, the register-transfer-level logic circuit into a gate-level logic circuit and to optimize the gate-level logic circuit, the program conducting the following steps of:
- extracting, using the register-transfer-level logic circuit as an input thereto, boundary sections from the register-transfer-level logic circuit;
- conducting, using the boundary sections extracted, first logic synthesis only for the boundary sections according to unit initial restriction;
- and
- executing, using a design resultant from the first logic synthesis, a first design budget according to the top restriction;
- said second process executing two times or more and comprising the following steps of:
- executing, using a timing restriction resultant from the first design budget, second logic synthesis;
- executing, using a design resultant from the second logic synthesis, a second design budget according to the top restriction;
- determining, according to timing restriction resultant from the second design budget, whether or not a timing violation is present;
- conducting, when a timing violation is present according to the timing restriction resultant from the second design budget, again the second logic synthesis using the timing restriction as an input thereto.
Dependencies are inferred from the claim text.