Programmable element latch circuit
AssigneeMicron Technology, Inc.
InventorGreg A. Blodgett
Life of this patent
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Abstract
An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.
Claims42
An programmable device, said device comprising:
- a programmable element;
- a latch for reading and holding a logic state of said programmable element;
- and
- a circuit coupled to said programmable element for simulating a programmed logic state of said programmable element, regardless of the actual programmed logic state of said programmable element.
An antifuse circuit comprising:
- an antifuse coupled to a source terminal of a first transistor;
- and
- an inverter coupled to a gate of said first transistor, said inverter selectively providing a signal to said first transistor to isolate said antifuse from a latch coupled to a drain of said first transistor;
- said latch receiving a signal for simulating a programmed logic state of said antifuse.
A processor system comprising:
- a processor;
- and
- a memory device coupled to said processor, said memory device containing at least one programmable device, said at least one programmable device comprising:
- a programmable element;
- a latch for reading and holding a logic state of said programmable element;
- and
- a circuit coupled to said programmable element for simulating a programmed logic state of said programmable element, regardless of the actual programmed logic state of said programmable element.
An integrated memory circuit comprising:
- a die containing a processor and memory device, said memory device containing at least one programmable device for selecting a redundant memory cell or column, said at least one programmable device comprising:
- a programmable element;
- a latch for reading and holding a logic state of said programmable element;
- and
- a circuit coupled to said programmable element for simulating a programmed logic state of said programmable element, regardless of the actual programmed logic state of said programmable element.
A method of simulating a programmed logic state of a programmable element, said method comprising:
- applying a first signal to an inverter to isolate said programmable element from a latch circuit;
- supplying a second signal to simulate a programmed logic state of said programmable element, regardless of the actual programmed logic state of said programmable element;
- and
- receiving said second signal for simulating said programmed logic state of said programmable element in said latch circuit to maintain said simulated programmed logic state.
A method of simulating an unblown antifuse in an antifuse latch device having a blown antifuse, said method comprising:
- applying a signal to an inverter;
- supplying a voltage in response to said signal to a gate of a transistor having a source terminal coupled to said antifuse in said antifuse latch device to simulate an unblown antifuse;
- and
- maintaining said simulation of a unblown antifuse by use of a latch circuit.
Dependencies are inferred from the claim text.