Method of designing layout of semiconductor device
AssigneeFujitsu Limited
InventorMasaki Komaki
Life of this patent
Estimating the term…
Abstract
This invention provides a method and system for designing the layout of a semiconductor device that appropriately arranges various types of auxiliary cells in vacant areas. The method of the present invention is devised for laying out a plurality of auxiliary cells between logic cells in a semiconductor device. The present invention further provides an apparatus comprising a processor configured to carry out the inventive method. The apparatus of the present invention may include a cell library in which the auxiliary cells are registered and dummy cells are utilized. The present invention additionally provides a computer readable storage medium, containing a program code instructed to perform the method of the present invention.
Claims26
A method for laying out at least one auxiliary cell in a vacant area that is not occupied by a logic cell in a semiconductor device, wherein each auxiliary cell includes at least one representative auxiliary cell and each auxiliary cell has a predetermined dimension, the method comprising:
- temporarily arranging each representative auxiliary cell in the vacant area;
- calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells;
- selecting at least one auxiliary cell based on the calculated number, the calculated total area, and a specification of the semiconductor device;
- and
- arranging the selected at least one auxiliary cell in place of the arranged representative auxiliary cells.
An apparatus for laying out at least one auxiliary cell in a vacant area that is not occupied by a logic cell in a semiconductor device, wherein each auxiliary cell includes at least one representative auxiliary cell and each auxiliary cell has a predetermined dimension, the apparatus comprising a processor for performing:
- temporarily arranging each representative auxiliary cell in the vacant area;
- calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells;
- selecting at least one auxiliary cell based on the calculated number, the calculated total area, and a specification of the semiconductor device;
- and
- arranging the selected at least one auxiliary cell in place of the arranged representative auxiliary cells.
A computer readable storage medium for storing a program that lays out at least one auxiliary cell in a vacant area that is not occupied by a logic cell in a semiconductor device, wherein each auxiliary cell includes at least one representative auxiliary cell and each auxiliary cell has a predetermined dimension, the program performing a process of:
- temporarily arranging each representative auxiliary cell in the vacant area;
- calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells;
- selecting at least one auxiliary cell based on the calculated number, the calculated total area, and a specification of the semiconductor device;
- and
- arranging the selected at least one auxiliary cell in place of the arranged representative auxiliary cells.
A computer readable transmission medium including a program code that lays out at least one auxiliary cell in a vacant area that is not occupied by a logic cell in a semiconductor device, wherein each auxiliary cell includes at least one representative auxiliary cell and each auxiliary cell has a predetermined dimension, the program code performing a process of:
- temporarily arranging each representative auxiliary cell in the vacant area;
- calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells;
- selecting at least one auxiliary cell based on the calculated number, the calculated total area, and a specification of the semiconductor device;
- and
- arranging the selected at least one auxiliary cell in place of the arranged representative auxiliary cells.
A method for laying out at least one auxiliary cell in a vacant area that is not occupied by a logic cell in a semiconductor device, wherein each auxiliary cell includes at least one representative auxiliary cell and each auxiliary cell has a predetermined dimension, the method comprising:
- temporarily arranging each representative auxiliary cell largest to smallest in dimension, in the vacant area;
- calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells;
- selecting at least one auxiliary cell based on the calculated number, the calculated total area, and a specification of the semiconductor device;
- and
- arranging the selected at least one auxiliary cell in place of the arranged representative auxiliary cells.
A method for laying out a plurality of auxiliary cells in a vacant area that is not occupied by a logic cell in a semiconductor device, wherein the plurality of auxiliary cells include at least one functional auxiliary cell, and the auxiliary cells are categorized into a plurality of groups based on a plurality of dimensions, the method comprising:
- temporarily arranging one or more representative auxiliary cells in the vacant area;
- calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells;
- selecting one or more of the functional auxiliary cells based on the calculated number, the calculated total area, and a specification of the semiconductor device;
- and
- arranging the selected one or more functional auxiliary cells in place of the arranged representative auxiliary cells.
An apparatus for laying out a plurality of auxiliary cells in a vacant area that is not occupied by a logic cell in a semiconductor device, wherein the plurality of auxiliary cells include at least one functional auxiliary cell, and the auxiliary cells are categorized into a plurality of groups based on a plurality of dimensions, the apparatus comprising a processor performing a process of:
- temporarily arranging one or more representative auxiliary cells in the vacant area;
- calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells;
- selecting one or more of the functional auxiliary cells based on the calculated number, the calculated total area, and a specification of the semiconductor device;
- and
- arranging the selected one or more functional auxiliary cells in place of the arranged representative auxiliary cells.
A computer readable storage medium for storing a program that lays out a plurality of auxiliary cells in a vacant area that is not occupied by a logic cell in a semiconductor device, wherein the plurality of auxiliary cells include at least one functional auxiliary cell, and the auxiliary cells are categorized into a plurality of groups based on a plurality of dimensions, the program performing a process of:
- temporarily arranging one or more representative auxiliary cells in the vacant area;
- calculating a number of the arranged representative auxiliary cells and a total area of the arranged representative auxiliary cells;
- selecting one or more of the functional auxiliary cells based on the calculated number, the calculated total area, and a specification of the semiconductor device;
- and
- arranging the selected one or more functional auxiliary cells in place of the arranged representative auxiliary cells.
Dependencies are inferred from the claim text.