Method of designing an integrated circuit memory architecture

A method of designing an integrated circuit memory architect wherein the memory architecture has a required memory capacity and determinable physical boundaries, the method comprising:

• defining a set of individual memory bank designs such that each individual memory bank design has a set of characteristics that is different than the set of characteristics of other individual memory bank designs;
• tiling selected individual memory bank designs to provide a memory array architecture comprising rows and columns of memory banks such that adjacent memory banks in the memory array architecture have matching dimensions along a common boundary and wherein address signals are routed between adjacent memory banks;
• and
• designing control circuitry to operationally couple with the memory banks, wherein the control circuitry is configured to generate addressing signals for selecting address locations from within the memory banks.