Method and apparatus for computing delay correlation effects in digital circuits
OwnerPeter Menegay, Daniel L. Notesteininventors
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Abstract
A method to automate techniques for using delay correlation effects to optimize the design of digital circuits, including a graphical method of data-entry and an optimized calculation scheme. It is used in conjunction with, or is part of, a computer program which performs timing analysis of digital circuits. The method calculates the time difference between two user-input timing paths in a circuit which include delay ranges for each gate in the paths along with correlation factors between any pair of gates. The method checks the user-input to determine an optimal calculation procedure. If none exists, it resorts to a calculation based on a sequential search of many possible timing states.
Claims6
A computer implemented method for performing a circuit timing analysis between any two paths of a timing chain using correlation information between timing relationships, including delays, setups, or holds, in a general fashion, comprising the steps of:
- identifying the timing relationships required by the analysis,
- listing all possible sequences of timing relationships in the analysis,
- deciding to maximize one of the timing paths while minimizing the other,
- and then selecting the sequence which produces minimum and maximum arrival times.
A computer implemented method for performing a circuit timing analysis between any two paths of a timing chain using correlation information between timing relationships, including delays, setups, or holds, in an optimized fashion, comprising the steps of:
- listing only unique pairs of correlation combinations between the paths, while ignoring the other correlation pairs,
- finding the arrival time of one path with respect to the other path for each correlation combination,
- and then summing the arrival times for all the correlation combinations, to produce the overall arrival time of a first path with respect to a second path.
A computer implemented method for performing a circuit timing analysis between any two paths of a timing chain using correlation information between timing relationships, including delays, setups or holds, in an optimized fashion, comprising the steps of:
- grouping all the delays using a single common delay correlation percentage,
- expressing the grouping of delays in each path as a single delay,
- and then finding the arrival time of a first path with respect to a second path in a single step.
A computer implemented method for performing a circuit timing analysis between any two paths of a timing chain using correlation information between timing relationships, including delays and constraints, comprising the steps of:
- accepting input of correlation information for the constraints,
- performing correlation analysis with the constraints,
- and then determining whether or not any constraints have been violated.
A computer implemented method for performing a circuit timing analysis using correlation information, comprising a step of grouping three or more timing relationships, including delays, setups, or holds, in such a manner that the correlation information is specified between all possible pairs in the grouping of timing relationships, by a set of the correlation information required by a single pair of timing relationships.
Dependencies are inferred from the claim text.