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US 6,553,549 B1Granted
Static timing analysis with simulations on critical path netlists generated by static timing analysis tools
AssigneeCypress Semiconductor Corporation
InventorsShiva P. Gowni, Rakesh Mehrotra
Life of this patent
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Abstract
A circuit comprising a plurality of gates and a plurality of control circuits. The plurality of gates may each have an output connected to an input of a next gate of the plurality of gates. The plurality of control circuits may be connected to a second input of one or more gates of the plurality of gates. The plurality of control circuits may simulate switching.
Claims20
An apparatus comprising:
- a plurality of gates having an output connected to an input of a next gate of said plurality of gates;
- and
- a plurality of control circuits connected to a second input of one or more gates of said plurality of gates, wherein said plurality of control circuits simulate switching of two or more of said inputs.
An apparatus comprising:
- means for controlling a plurality of gates having an output connected to an input of a next gate of said plurality of gates;
- and
- means for controlling a plurality of control circuits connected to a second input of one or more gates of said plurality of gates, wherein (i) said control circuits simulate switching and (ii) said plurality of gates simulate switching of two or more of said inputs.
A method for generating a netlist simulation comprising the steps of:
- (A) simulating the switching of a plurality of gates having an output connected to an input of a next gate of said plurality of gates;
- and
- (B) controlling the switching of two or more gates of said plurality of gates by simulating switching of two or more of said inputs of said gates.
A computer readable medium containing instructions for generating a netlist simulation comprising:
- (A) simulating the switching a plurality of gates having an output connected to an input of a next gate of said plurality of gates;
- and
- (B) controlling the switching one or more gates of said plurality of gates by simulating switching of two or more of said inputs of said gates.
Dependencies are inferred from the claim text.