Failure analyzing apparatus and failure analyzing method for semiconductor integrated circuit

A failure analyzing method for a semiconductor integrated circuit, comprising:

• operating a good semiconductor integrated circuit chip and a target semiconductor integrated circuit chip to be subjected to failure analysis by supplying test signals to said good semiconductor integrated circuit chip and said target semiconductor integrated circuit chip from a testing device;
• detecting an emission image formed by hot electrons emitted from said good semiconductor integrated circuit chip and an emission image formed by hot electrons emitted from said target semiconductor integrated circuit chip using an emission analyzer;
• and
• specifying a failure location in said target semiconductor integrated circuit chip by performing image processing on both emission images detected.

A failure analyzing apparatus for a semiconductor integrated circuit, comprising:

• a function tester for generating test signals and supplying said test signals to a semiconductor integrated circuit chip to execute a function test thereof;
• an emission analyzer for detecting an emission image formed by hot electrons emitted from said semiconductor integrated circuit chip when said function test is performed by said function tester;
• an image processing device, connected to said emission analyzer, for specifying a failure location in a target semiconductor integrated circuit chip to be subjected to failure analysis, based on an emission image of a good semiconductor integrated circuit chip detected by said emission analyzer and an emission image of said target semiconductor integrated circuit chip;
• and
• a display device, connected to said image processing device, for displaying said failure location specified by said image processing device.

A failure analyzing apparatus for a semiconductor integrated circuit, comprising:

• a function tester for generating supply voltages and test signals and supplying said supply voltages and said test signals to a semiconductor integrated circuit chip to execute a function test thereof;
• an emission analyzer for detecting an emission image by integrating hot electrons emitted from said semiconductor integrated circuit chip when said function test is performed by said function tester, an integration time for said hot electrons being variable;
• an image processing device, connected to said emission analyzer, for specifying a failure location in a target semiconductor integrated circuit chip to be subjected to failure analysis, based on an emission image of a good semiconductor integrated circuit chip detected by said emission analyzer and an emission image of said target semiconductor integrated circuit chip;
• a display device, connected to said image processing device, for displaying said failure location specified by said image processing device;
• and
• a condition providing device for altering an operational condition by variously changing at least a value of said supply voltages generated by said function tester and/or said integration time for hot electrons in said emission analyzer, causing said function tester to operate said target semiconductor integrated circuit chip in each alteration to check a number of occurrences of false emission caused by emission images detected by said emission analyzer, and acquiring that operational condition under which said number of occurrences of false emission becomes equal to or smaller than a predetermined value, whereby an operation of said function tester and/or an operation of said emission analyzer is controlled based on said operational condition acquired by said condition providing device.

A failure analyzing apparatus for a semiconductor integrated circuit, comprising:

• a function tester for generating supply voltages and test signals and supplying said supply voltages and said test signals to a semiconductor integrated circuit chip to execute a function test thereof;
• an emission analyzer for detecting an emission image by integrating hot electrons emitted from said semiconductor integrated circuit chip when said function test is performed by said function tester, an integration time for said hot electrons being variable;
• an image processing device, connected to said emission analyzer, for specifying a failure location in a target semiconductor integrated circuit chip to be subjected to failure analysis, based on an emission image of a good semiconductor integrated circuit chip detected by said emission analyzer and an emission image of said target semiconductor integrated circuit chip, and outputting coordinate data of said failure location;
• a display device, connected to said image processing device, for displaying said failure location specified by said image processing device;
• a condition providing device for altering an operational condition by variously changing at least a value of said supply voltages generated by said function tester and/or said integration time for hot electrons in said emission analyzer, causing said function tester to operate said target semiconductor integrated circuit chip in each alteration to check a number of occurrences of false emission caused by emission images detected by said emission analyzer, and acquiring that operational condition under which said number of occurrences of false emission becomes equal to or smaller than a predetermined value, whereby an operation of said function tester and/or an operation of said emission analyzer is controlled based on said operational condition acquired by said condition providing device;
• a navigation device, connected to said image processing device, for storing net data and coordinate data of said target semiconductor integrated circuit chip and generating node data and coordinate data which are associated with a node of a preceding circuit of a node corresponding to said coordinate data output from said image processing device;
• a potential measuring device, connected to said navigation device, for measuring a potential of a surface of said semiconductor integrated circuit at a position corresponding to said coordinate data generated by said navigation device;
• a potential comparing device, connected to said potential measuring device and said navigation device, for storing expected value data of potentials at all nodes of said target semiconductor integrated circuit chip and comparing said potential measured by said potential measuring device with an expected value of a node corresponding to said node data provided by said navigation device;
• and
• a coordinate data outputting device, connected to said potential comparing device, for outputting coordinate data of said node corresponding to said node data provided by said navigation device to said display device as coordinate data corresponding to a failure location in said target semiconductor integrated circuit chip when said potential measured by said potential measuring device does not match with said expected value of said node corresponding to said node data provided by said navigation device.