Semiconductor device extractor for electrostatic discharge and latch-up applications
AssigneeTexas Instruments Incorporated
InventorsSridhar Ramaswamy, Snehamay Sinha, Gopalarao Kadamati, Ranjit Gharpurey
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Abstract
For simulating electrostatic discharge and latch-up in semiconductor devices, the disclosed system and method for extracting parasitic devices combine input data from device layout, technology rules and doping profiles in order to extract netlists, element location and substrate resistance, analyze the layout for parasitic device formation, store these lists in a verification data base, translate the data base into a specific format, and finally output lists of ESD- and latch-up-sensitive elements and their locations in a specific format such as SPICE format.
Claims11
A computerized system for minimizing electrostatic discharge (ESD) and latch-up sensitivities in a semiconductor circuit design, comprising:
- an input data generator operable to generate information describing circuit layout, technology rules, process results, and ESD rules;
- a device extractor, coupled to said input data generator, operable to extract netlist, locations and parasitic substrate resistance data, as analyzed by said rules;
- a verification data base, coupled to said device extractor, operable to store said netlist, locations list and resistance list into said verification database;
- a translator, coupled to said verification data base, operable to generate said netlist, locations list and resistance list in a specific format from said verification database;
- an output data generator, coupled to said translator, operable to create netlists and location lists of parasitic, ESD- and latch-up-sensitive elements, said lists expressed in specific formats or displays.
A computer-implemented method for minimizing electrostatic discharge and latch-up sensitivities in a semiconductor device design, comprising the steps of:
- generating input data describing circuit layout, rules for technology, ESD and latch-up, and process results used in said design of said semiconductor device;
- extracting netlist, locations and parasitic substrate resistance lists from said input data;
- analyzing said extracted lists against said rules for ESD and latch-up;
- storing said netlist, locations list and resistance list into a verification database;
- generating said netlist, locations list and resistance list in a specific format from said verification data base;
- and
- creating summary netlists and locations lists of parasitic and ESD- and latch-up-sensitive elements, said lists expressed in specific formats or displays.
Dependencies are inferred from the claim text.