Integrated circuit devices that include self-test apparatus for testing a plurality of functional blocks and methods of testing same

An integrated circuit device, comprising:

• a first test pattern unit that produces a sequence of n-bit input data patterns;
• a second test pattern unit that produces a sequence of m-bit input data patterns;
• a first plurality of test blocks that are connected in parallel to the first test pattern unit;
• a second plurality of test blocks that are connected in parallel to the second test pattern unit;
• a control unit that selects a first test block from the first plurality of test blocks, the first test block being responsive to the sequence of n-bit input data patterns to generate a first sequence of output data patterns, and selects a second test block from the second plurality of test blocks, the second test block being responsive to the sequence of m-bit input data patterns to generate a second sequence of output data patterns;
• a first data compression unit responsive to the first sequence of output data patterns that generates a first signature;
• and
• a second data compression unit responsive to the second sequence of output data patterns that generates a second signature.

A method of testing an integrated circuit device having a plurality of test blocks, comprising the steps of:

• generating a sequence of input data patterns;
• providing the sequence of input data patterns to the plurality of test blocks in parallel;
• selecting a test block from the plurality of test blocks;
• and
• compressing a sequence of output data patterns, which are produced by the selected test block in response to the sequence of input data patterns, into a signature.

A method of testing an integrated circuit device having a first plurality of test blocks having n input terminals and a second plurality of test blocks having m input terminals, comprising the steps of:

• generating a sequence of n-bit input data patterns;
• providing the sequence of n-bit input data patterns to the first plurality of test blocks in parallel;
• selecting a first test block from the first plurality of test blocks;
• compressing a first sequence of output data patterns, which are produced by the first test block in response to the sequence of n-bit input data patterns, into a signature;
• generating a sequence of m-bit input data patterns;
• providing the sequence of m-bit input data patterns to the second plurality of test blocks in parallel;
• selecting a second test block from the second plurality of test blocks;
• and
• compressing a second sequence of output data patterns, which are produced by the second test block in response to the sequence of m-bit input data patterns, into a signature.