Low cost timing system for highly accurate multi-modal semiconductor testing
AssigneeTeradyne, Inc.
InventorPeter Reichert
Life of this patent
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Abstract
A timing system is disclosed that responds to pattern generation circuitry for producing test patterns for application to a device-under-test. The timing system includes a timing memory circuit that stores programmed edge timings for the patterns and couples to timing logic including a master oscillator and a plurality of fixed edge generators. The fixed edge generators are responsive to the programmed edge timings to produce the event timing signals.
Claims18
A semiconductor tester for testing a device-under-test having a combination of high-speed and low-speed pins, said tester including:
- a test controller having a pattern memory and a user interface;
- a pattern generation circuit having respective high-speed and low-speed modes for selectively producing test patterns according to said pattern memory for application to said device-under-test, said device-under-test operating according to a DUT clock period;
- a system bus connected to said test controller and said pattern generation circuit for routing command and data signals therebetween;
- drive/compare circuitry adapted for coupling to said device-under-test;
- a failure processing circuit disposed between said system bus and said drive/compare circuitry;
- and
- a timing system to generate event timing signals corresponding to predefined user settings, said timing system including:
- a timing memory circuit for storing programmed edge timings for said patterns;
- and
- timing logic including a master oscillator and a plurality of fixed edge generators, said fixed edge generators responsive to said programmed edge timings to produce said event timing signals.
A method of generating timing signals consistent with user-defined settings for a device-under-test, said DUT having high-speed pins and low-speed pins, said timing signals generated by a timing system responsive to a multi-mode pattern generation circuit and including a timing memory and timing logic including a plurality of fixed edge generators, said method including the steps of:
- assigning said fixed edge generators to produce a fixed number of edge timings corresponding to said edge generators within said DUT period in said high-speed mode;
- applying high-speed patterns to said DUT high-speed pins in accordance with said operating DUT period;
- distributing said fixed-edge generators to produce a selection of edge timings per master oscillator period.
Dependencies are inferred from the claim text.