Programmable array built-in self test method and system for arrays with imbedded logic

A programmable ABIST (PABIST) method for testing an imbedded logic array comprising the steps of:

• (1) executing a PABIST first method for testing an imbedded logic array, said first method further comprising the steps of:
• scanning into a programmable ABIST controller a test instruction sequence;
• executing said test instruction sequence;
• outputting, in response to executing each instruction step in said test instruction sequence, first control bits and second control bits and coupling said first control bits to an expect data generator and coupling said second control bits to an input address generator and an input data generator for said imbedded logic array;
• generating expect data outputs from said expect data generator in response to said first control bits concurrent with generating input addresses from said input address generator and input data from said input data generator in response to said second control bits;
• generating outputs of said imbedded logic array in response to said input addresses and said input data;
• comparing said expect data outputs, said outputs of said imbedded logic array, and selected control bits from said first control bits;
• and
• generating and outputting a sequence of pass/fail results in response to said comparison of said expect data outputs, said outputs of said imbedded logic array and said selected control bits;
• (2) analyzing said pass/fail results of said first test method and configuring logic test instruction sequences for testing said imbedded logic array;
• and
• (3) executing a second test method, said second test method comprising the steps of:
• scanning into said PABIST controller said logic test instruction sequences via a level sensitive scan device (LSSD);
• executing said logic test instruction sequences;
• writing a specified first data pattern to all addresses of said imbedded logic array;
• writing to one or more addresses of said imbedded logic array with a specified second data pattern followed by reading said imbedded logic array while selecting all of said imbedded logic array addresses concurrently;
• comparing logic expected data outputs and imbedded logic array outputs from said imbedded logic array;
• and
• generating and outputting a sequence of pass/fail results in response to a compare of said logic expected data outputs and said imbedded logic array outputs.

An Array Built-In-Self-Test (ABIST) system for testing an imbedded logic array comprising:

• ABIST control circuitry for generating array input addresses, array input data, and array read/write controls;
• a circuit operable to generate logic expect output data;
• a circuit operable to select concurrently all addresses of said imbedded logic array during a read of said imbedded logic array;
• and
• a data comparator for comparing imbedded logic array output data from said imbedded logic array and said logic expect output data, said data comparator generating pass/fail results of said comparing of said imbedded logic array output data and said logic expect output data.

A programmable ABIST (PABIST) system for testing an imbedded logic array comprising:

• a PABIST controller for generating input address control bits, input data control bits, read/write control bits, and expect control bits in response to executing programmed instructions;
• a programmable expect generator (PEG), said PEG receiving said expect control bits and generating corresponding expect output data in response to said expect control bits;
• a data comparator, said data comparator comparing imbedded logic array output data from said imbedded logic array, said expect output data, and selected expect control bits of said expect control bits, said data comparator generating pass/fail results of said comparing of said imbedded logic array output data, said expect output data and said selected expect control bits;
• and
• a circuit operable to select concurrently all addresses of said imbedded logic array during a read of said imbedded logic array.

A data processing system, comprising:

• a central processing unit (CPU);
• random access memory (RAM);
• read only memory (ROM);
• an I/O adapter;
• and
• a bus system coupling said CPU to said ROM, said RAM and said I/O adapter, wherein said CPU and said RAM further comprise imbedded logic arrays with Array Built-In-Self-Test (ABIST), said ABIST comprising:
• ABIST control circuitry for generating array input address control bits, array input data control bits, expect control bits and array read/write control bits in response to programmed instructions;
• a circuit operable to generate logic expect output data;
• a circuit operable to select concurrently all addresses of said imbedded logic array during a read of said imbedded logic array;
• and
• a data comparator, said data comparator comparing imbedded logic array output data from one of said imbedded logic arrays, said logic expect output data, said data comparator generating pass/fail results of said comparing of said imbedded logic array output data and said logic expect output data.

A data processing system, comprising:

• a central processing unit (CPU);
• random access memory (RAM);
• read only memory (ROM);
• an I/O adapter;
• and
• a bus system coupling said CPU to said ROM, said RAM and said I/O adapter, wherein said CPU and said RAM further comprise imbedded logic arrays with programmable Array Built-In-Self-Test (PABIST), said PABIST comprising;
• a PABIST controller for generating array input address control bits, array input data control bits, read/write control bits, and expect control bits in response to executing programmed instructions;
• a programmable expect generator (PEG), said PEG receiving said expect control bits and generating corresponding expect output data in response to said expect control bits;
• a data comparator for comparing imbedded logic array output data from one of said imbedded logic arrays, said expect output data, and selected expect control bits of said expect control bits, said data comparator generating pass/fail results of said comparing of said imbedded logic array output data, said expect output data and said selected expect control bits;
• and
• a circuit operable to select concurrently all addresses of said imbedded logic array during a read of said imbedded logic array.