Method and apparatus for selectively enabling and disabling functions on a per array basis
AssigneeInternational Business Machines Corporation
InventorPhilip George Shephard, III
Life of this patent
Estimating the term…
Abstract
A method and apparatus for testing a plurality arrays on a processor with an on chip built in self test engine on the processor. A subset of the plurality arrays on the processor is selected for testing using a control mechanism to selectively enable testing of the subset. Data patterns from the on chip built in self test engine are sent to the plurality arrays on the processor. A response is received at the on chip built in self test engine from the plurality arrays. The response from the plurality arrays is compared to an expected response using the on chip built in self test engine.
Claims21
A built-in on-chip test system comprising:
- a set of arrays having input ports and data output ports;
- a test logic connected to the set of arrays, wherein the test logic tests the set of arrays by sending test data into the input ports to access the set of arrays, wherein results are generated at the data output ports of the set of arrays and comparing the results from the set of arrays to an expected result for the set of arrays;
- and
- a control logic connected to the set of arrays, wherein the control logic selectively enables testing of selected arrays within the set of arrays using test data corresponding to the selected arrays.
A built-in on-chip test system comprising:
- a set of arrays having input ports and data output ports;
- a test logic connected to the set of arrays, wherein the test logic tests the set of arrays by sending test data into the input ports to access the set of arrays, wherein results are generated at the data output ports of the set of arrays and comparing the results from the set of arrays to an expected result for the set of arrays;
- and a control logic connected to the set of arrays, wherein the control logic selectively enables testing of selected arrays within the set of arrays, wherein the built-in on-chip test system includes an array built in self test engine comprising:
- a data control register for generating and applying deterministic data patterns to the data input ports of each array within the set of arrays;
- an address control register for generating addresses for application to each array within the set of arrays in coordination with the data control register;
- and
- a comparator for comparison of data input to said data input ports of each array within the set of arrays from the data control register with data output from the data output ports of each array within the set of arrays.
A method for testing a plurality of arrays on a processor with an on a built in self test engine on the processor, the method comprising:
- selecting a subset of the plurality of arrays for testing;
- sending data patterns corresponding to the subset of the plurality of arrays from the on chip built in self test engine to the plurality arrays on the processor;
- receiving a response at the on chip built in self test engine from the plurality of arrays;
- and
- comparing the response from the plurality of arrays to an expected response using the on chip built in self test engine.
An apparatus for testing a plurality of arrays on a processor with an on chip built in self test engine on the processor, the apparatus comprising:
- selecting means for selecting a subset of the plurality of arrays for testing;
- sending means for sending data patterns corresponding to the subset of the plurality of arrays from the on chip built in self test engine to the plurality of arrays on the processor;
- receiving means for receiving a response at the on chip built in self test engine from the plurality of arrays;
- and
- comparing means for comparing the response from the plurality of arrays to an expected response using the on chip built in self test engine.
A computer program product in a computer readable medium for testing a plurality of arrays on a processor with an on chip built in self test engine on the processor, the computer program product comprising:
- first instructions for selecting a subset of the plurality of arrays for testing;
- second instructions for sending data patterns corresponding to the subset of the plurality of arrays from the on chip built in self test engine to the plurality of arrays on the processor;
- third instructions for receiving a response at the on chip built in self test engine from the plurality of arrays;
- and
- fourth instructions for comparing the response from the plurality of arrays to an
Dependencies are inferred from the claim text.