Method for automating validation of integrated circuit test logic

A computer readable medium containing executable instructions which, when executed in a processing system, causes the system to automatically validate test hardware of an integrated circuit device, comprising:

• a) instructions for extracting and validating a test hardware portion of connectivity of the integrated circuit device, comprising:
• 1) during a first extraction procedure, instructions for validating the connectivity of a plurality of test signals, residing at a plurality of test signal output ports of a test control block of the test hardware portion comprised of a plurality of serially-connected scan latch instances, to the plurality of serially-connected scan latch instances;
• 2) instructions for generating and logging any test signal connectivity errors identified during validating the connectivity of the plurality of test signals to the plurality of serially-connected scan latch instances;
• 3) during a second extraction procedure, instructions for validating the inter-connectivity of the plurality of serially-connected scan latch instances;
• and
• 4) instructions for generating and logging any scan latch inter-connectivity errors identified during validating the inter-connectivity of the plurality of serially-connected scan latch instances;
• b) instructions for representing the extracted and validated test hardware portion of the connectivity of the test hardware in a block description language;
• c) instructions for using any logged test signal connectivity errors and any scan latch inter-connectivity errors to improve the test hardware portion.

A method for automatic validation of test hardware of an integrated circuit device, comprising:

• a) extracting and validating a test hardware portion of connectivity of the integrated circuit device, comprising:
• 1) for each test signal output port of a plurality of test signal output ports of a test control block of the test hardware portion, comprising:
• A) for a test signal output port of the plurality of test signal output ports of the test control block, assigning a test signal output port signal type;
• B) for an instance of a plurality of instances of the test hardware portion designated as being permissible to traverse and to which a test signal resident at the test signal output port will fan out to, traversing through the instance to determine if the instance is a scan latch instance of a plurality of scan latch instances of the test hardware portion;
• C) if the instance is a scan latch instance, determining whether the test signal that has traversed to a scan latch port of a plurality of scan latch ports of the scan latch instance is of a type that is properly provided to the scan latch port, wherein if the type of the test signal is not of a type that is properly provided to the scan latch port generating and logging a test signal type error;
• D) if the instance is not a scan latch instance, comprising:
• i) for every port of a plurality of ports of the instance that is designated as being permissible to traverse assigning a signal type based upon an instance type of the instance and a type of an input signal to the instance;
• ii) traversing the plurality of ports of the instance to identify a first plurality of new instances to which a plurality of test signals resident at the plurality of ports will flow;
• and
• iii) performing a1Di)-a1Dii) for each new instance of the first plurality of new instances identified;
• E) determining whether each instance of the plurality of instances to which the test signal resident at the test signal output port will fan out to and that has been designated as being permissible to traverse has been traversed;
• F) if each instance of the plurality of instances has not been traversed, returning to a1B)) to traverse another, untraversed instance of the plurality of instances designated as being permissible to traverse;
• G) if each instance of the plurality of instances has been traversed, returning to a1A) if a1A) to a1E) has not been performed for each test signal output port of the plurality of test signal output ports;
• H) generating and logging any test signal connectivity errors identified during a1A) to a1G);
• 2) for each test data output port of a plurality of test data output ports of the test control block of the test hardware portion, comprising:
• A) for an instance of a plurality of instances of the test hardware portion designated as being permissible to traverse and to which a test data signal resident at the test data output port will fan out to, traversing through the instance to determine if the instance is a scan latch instance of the plurality of scan latch instances of the test hardware portion;
• B) if the instance is a scan latch instance, performing an electrical quality check of the scan latch instance and logging any electrical quality errors and determining whether each scan latch port of the plurality of scan latch ports of the scan latch instance have been previously traversed during a1A)-a1H);
• C) if each scan latch port of the plurality of scan latch ports of the scan latch instance has not been previously traversed during a1), generating and logging a scan latch port error for each scan latch port that has not been previously traversed;
• D) traversing a plurality of data output ports of the instance that is designated as being permissible to traverse to identify a second plurality of new instances to which a plurality of test data signals resident at the plurality of data output ports will flow;
• E) performing a2B)-a2E) for each new instance of the second plurality of new instances identified in a2D);
• F) determining whether each instance of the plurality of instances to which the data signal will fan out to and that has been designated as being permissible to traverse has been traversed;
• G) if each instance of the plurality of instances has not been traversed, returning to a2A) to traverse another, untraversed instance of the plurality of instances designated as being permissible to traverse;
• H) if each instance of the plurality of instances has been traversed, returning to a2) if a2A) to a2G) has not been performed for each test data output port of the plurality of output test ports of the test control block;
• and
• I) generating and logging any scan latch inter-connectivity errors identified during a2A) to a2H);
• 3) for each scan latch instance traversed in a1) but not in a2), generating and logging a scan latch floating error to generate a plurality of scan latch floating errors;
• b) representing the extracted and validated test hardware portion of the connectivity of the test hardware in a block description language;
• and
• c) using any logged test signal connectivity errors, scan latch inter-connectivity errors, and scan latch floating errors to improve the test hardware portion.

A computer readable medium containing executable instructions which, when executed in a processing system, causes the system to automatically validate test hardware of an integrated circuit device, comprising:

• a) instructions for extracting and validating a test hardware portion of connectivity of the integrated circuit device, comprising:
• 1) for each test signal output port of a plurality of test signal output ports of a test control block of the test hardware portion, comprising:
• A) for a test signal output port of the plurality of test signal output ports of the test control block, instructions for assigning a test signal output port signal type;
• B) for an instance of a plurality of instances of the test hardware portion designated as being permissible to traverse and to which a test signal resident at the test signal output port will fan out to, instructions for traversing through the instance to determine if the instance is a scan latch instance of a plurality of scan latch instances of the test hardware portion;
• C) if the instance is a scan latch instance, instructions for determining whether the test signal that has traversed to a scan latch port of a plurality of scan latch ports of the scan latch instance is of a type that is properly provided to the scan latch port, wherein if the type of the test signal is not of a type that is properly provided to the scan latch port generating and logging a test signal type error;
• D) if the instance is not a scan latch instance, comprising:
• i) for every port of a plurality of ports of the instance that is designated as being permissible to traverse instructions for assigning a signal type based upon an instance type of the instance and a type of an input signal to the instance;
• ii) instructions for traversing the plurality of ports of the instance to identify a first plurality of new instances to which a plurality of test signals resident at the plurality of ports will flow;
• and
• iii) instructions for performing 1Di)-1Diii) for each new instance of the first plurality of new instances identified;
• E) instructions for determining whether each instance of the plurality of instances to which the test signal resident at the test signal output port will fan out to and that has been designated as being permissible to traverse has been traversed;
• F) if each instance of the plurality of instances has not been traversed, returning to a1B)) to traverse another, untraversed instance of the plurality of instances designated as being permissible to traverse;
• G) if each instance of the plurality of instances has been traversed, returning to a1A) if a1A) to a1E) has not been performed for each test signal output port of the plurality of test signal output ports;
• H) instructions for generating and logging any test signal connectivity errors identified during a1A) to a1G);
• 2) for each test data output port of a plurality of test data output ports of the test control block of the test hardware portion, comprising:
• A) for an instance of a plurality of instances of the test hardware portion designated as being permissible to traverse and to which a test data signal resident at the test data output port will fan out to, instructions for traversing through the instance to determine if the instance is a scan latch instance of the plurality of scan latch instances of the test hardware portion;
• B) if the instance is a scan latch instance, instructions for performing an electrical quality check of the scan latch instance and logging any electrical quality errors and instructions for determining whether each scan latch port of the plurality of scan latch ports of the scan latch instance have been previously traversed during a1A)-a1H);
• C) if each scan latch port of the plurality of scan latch ports of the scan latch instance has not been previously traversed during a1), instructions for generating and logging a scan latch port error for each scan latch port that has not been previously traversed;
• D) instructions for traversing a plurality of data output ports of the instance that is designated as being permissible to traverse to identify a second plurality of new instances to which a plurality of test data signals resident at the plurality of data output ports will flow;
• E) performing a2B)-a2E) for each new instance of the second plurality of new instances identified in a2D);
• F) instructions for determining whether each instance of the plurality of instances to which the data signal will fan out to and that has been designated as being permissible to traverse has been traversed;
• G) if each instance of the plurality of instances has not been traversed, returning to a2A) to traverse another, untraversed instance of the plurality of instances designated as being permissible to traverse;
• H) if each instance of the plurality of instances has been traversed, returning to a2) if a2A) to a2G) has not been performed for each test data output port of the plurality of output test ports of the test control block;
• and
• I) instructions for generating and logging any scan latch inter-connectivity errors identified during a2A) to a2H);
• 3) for each scan latch instance traversed in a1) but not in a2), instructions for generating and logging a scan latch floating error to generate a plurality of scan latch floating errors;
• b) instructions for representing the extracted and validated test hardware portion of the connectivity of the test hardware in a block description language;
• and
• c) using any logged test signal connectivity errors, scan latch inter-connectivity errors, and scan latch floating errors to improve the test hardware portion.