Valuation of tester accuracy
AssigneeSchlumberger Technologies, Inc.
InventorsWajih Dalal, Song Miao
Life of this patent
Estimating the term…
Abstract
Tester edge placement accuracy (EPA) is important for testing of semiconductor component devices. The value of that accuracy is quantified to the device manufacturer in terms of yield loss and bad parts sold as good parts (escapes in DPM). A simulation is presented that models the tester accuracy, the device edge distribution and their interaction for a example device having an operating speed of 800 Mbps. The same model can be applied for microprocessors or other parts that operate near the limits of ATE performance. In an example given, the estimated losses due to lack of appropriate tester accuracy are considerable: with the estimated yields and selling prices for the example device, the model shows a value of over $1 M for every 1 ps of enhanced tester edge placement accuracy.
Claims13
A method of comparing a first semiconductor component tester having a first overall tester accuracy with a second semiconductor component tester having a second overall tester accuracy, comprising:
- a. Calculating actual yield of the first semiconductor component tester for a given set of input parameters;
- b. Calculating actual yield of the second semiconductor component tester for the given set of input parameters;
- c. Comparing the actual yield of the first semiconductor component tester with the actual yield of the second semiconductor component tester.
A method of estimating actual yield of a semiconductor device tester, comprising:
- a. setting input parameters, including an acceptable defect rate;
- b. assuming a normal distribution of signal edge placement versus time, calculate standard deviation of signal edge placement (σ_dut) about the mean signal edge placement (μ_dut);
- c. initializing a test limit;
- d. calculating an expected defect rate;
- and
- e. calculating actual yield.
A computer program product for comparing a first semiconductor component tester having a first overall tester accuracy with a second semiconductor component tester having a second overall tester accuracy, comprising:
- a. instructions for calculating actual yield of the first semiconductor component tester for a given set of input parameters;
- b. instructions for calculating actual yield of the second semiconductor component tester for the given set of input parameters;
- and
- c. instructions for comparing the actual yield of the first semiconductor component tester with the actual yield of the second semiconductor component tester.
A computer system for comparing a first semiconductor component tester having a first overall tester accuracy with a second semiconductor component tester having a second overall tester accuracy, comprising:
- a. Program code for calculating actual yield of the first semiconductor component tester for a given set of input parameters;
- b. Program code for calculating actual yield of the second semiconductor component tester for the given set of input parameters;
- and
- c. Program code for comparing the actual yield of the first semiconductor component tester with the actual yield of the second semiconductor component tester.
An article of manufacture comprising a computer readable medium encoded with a computer program for comparing a first semiconductor component tester having a first overall tester accuracy with a second semiconductor component tester having a second overall tester accuracy, the computer program comprising:
- a. Instructions for calculating actual yield of the first semiconductor component tester for a given set of input parameters;
- b. Instructions for calculating actual yield of the second semiconductor component tester for the given set of input parameters;
- c. Instructions for comparing the actual yield of the first semiconductor component tester with the actual yield of the second semiconductor component tester.
A computer program product for estimating actual yield of a semiconductor device tester, comprising:
- a. Instructions for setting input parameters, including an acceptable defect rate;
- b. Instructions for calculating standard deviation of signal edge placement (σ_dut) about the mean signal edge placement (μ_dut), assuming a normal distribution of signal edge placement versus time;
- c. Instructions for initializing a test limit;
- d. Instructions for calculating an expected defect rate;
- and
- e. Instructions for calculating actual yield.
Dependencies are inferred from the claim text.