Digital circuit verification
AssigneeInternational Business Machines Corporation
InventorsJason Raymond Baumgartner, Nadeem Malik, Steven Leonard Roberts
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AssigneeInternational Business Machines Corporation
InventorsJason Raymond Baumgartner, Nadeem Malik, Steven Leonard Roberts
Estimating the term…
A method of verifying a digital circuit in which state transition information is extracted from the output of a non-formal first verification technique. A formal verification tool is then applied to the extracted state transition information to extend the verification coverage of the digital circuit beyond the coverage that is achieved using the first verification technique. In one embodiment, the method includes the initial step of applying a first verification technique such as a simulation technique to a model of the digital circuit. In the preferred embodiment, the application of the formal verification tool comprises applying a model checker to the extracted state transition data to achieve a formal verification of the state machine represented by the state transition diagram. In one embodiment, the extracted state transition information includes a set of data points each representing a present state, a present input, and a next state. In one embodiment useful for extending the verification coverage provided by a conventional non-formal verification technique, the non-formal tool is used to verify satisfaction of a specification or rule by traversing a first transition path of the circuit. The non-formal tool is then used a second time to verify the rule or specification by traversing a second transition path. State transition information generated during the first and second passes of the non-formal verification technique is then extracted and provided to a formal verification tool such as a model checker. The formal verification of the circuit represented by the extracted state transition information extends the verification coverage achieved with the non-formal verification tool such as by, for example, traversing the digital circuit with a third transition path that was not explored with the non-formal verification tool. In addition, infinite loop conditions or live lock conditions may be detected by applying the formal verification technique to the extracted state transition information. Extraction and archiving of transition information may be performed periodically to accumulate new transition information.
A method of verifying a digital circuit, comprising:
A computer program product, stored on a computer readable medium and suitable for executing on a computer, for verifying a digital circuit, the computer program product comprising:
A computer system including processor, memory, input, and display, the memory configured with computer useable code means for:
Dependencies are inferred from the claim text.