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US 6,553,512 B1Granted
Method and apparatus for resolving CPU deadlocks
AssigneeHewlett-Packard Development Company, L.P.
InventorJames Douglas Gibson
Life of this patent
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AssigneeHewlett-Packard Development Company, L.P.
InventorJames Douglas Gibson
Estimating the term…
A method and apparatus for handling errors that deadlock a CPU by first attempting to resolve the deadlock without issuing a bus error and without restarting the CPU. If the deadlock cannot be resolved without issuing a bus error, then a bus error is issued and the CPU attempts to restart. The method involves comparing the number of clock cycles taken to execute an instruction to a designated abort value. When an instruction has taken the full abort value of cycles but has not retired, a machine-check abort (MCA) is issued to attempt to resolve the deadlock. The method also involves comparing the number of clock cycles to a larger bus error value. If the MCA does not break the deadlock within a certain period—i.e., before the bus error value is reached—then a bus error is issued and the machine attempts to reset.
A method for handling CPU deadlock comprising:
A method for resolving a deadlock in a mixed-architecture CPU, comprising:
A method for resolving a deadlock in a mixed-architecture CPU, comprising:
A computer system comprising:
The computer system of 14, wherein the CPU supports a plurality of instruction sets.
Dependencies are inferred from the claim text.