Method and apparatus for performing clock timing de-skew

An apparatus for performing timing de-skew, comprising:

• a generating portion for generating N sequences of clock pulses, the generated sequences of clock pulses having phases offset from one another by intervals of T/N, where N is at least 2 and T is a duration of one bit-cell time, and where one cycle of each of the sequences has a duration of 2T;
• a transmitting portion for transmitting a test signal;
• a receiving portion for receiving the test signal, the receiving portion comprising:
• a data receiver for receiving bits of the test signal;
• an identifying portion for receiving the bits of the test signal from the data receiver and identifying which one of the generated sequences of clock pulses and corresponding polarities has aligned with rising and falling edges of the test signal;
• and
• a determining mechanism to use the identified one of the generated sequences of clock pulses and the corresponding polarities to determine another one of the generated sequences of clock pulses and the corresponding polarities to use to receive digital computer information.

A method of providing a de-skewed clock signal, comprising:

• receiving a test signal;
• receiving a clock signal;
• generating delayed clock signals in response to the clock signal, wherein the delayed clock signals are offset from one another by less than one bit-cell time of the clock signal;
• identifying one of the delayed clock signals that is aligned with the test signal as an aligned clock signal;
• and
• providing another one of the delayed clock signals as the de-skewed clock signal in response to the aligned clock signal.

A method of providing a de-skewed clock signal, comprising:

• receiving a test signal from a parallel data bus, wherein the test signal has a bit-cell time;
• receiving a clock signal from the parallel data bus, wherein the clock signal has the bit-cell time;
• generating delayed clock signals in response to the clock signal, wherein the delayed clock signals are offset from one another by intervals of T/N, where N is at least 2 and T is the bit-cell time;
• identifying one of the delayed clock signals as an aligned clock signal, wherein edges of the aligned clock signal are aligned with rising and falling edges of the test signal;
• and
• providing another one of the delayed clock signals as the de-skewed clock signal in response to the aligned clock signal.

A method of providing a de-skewed clock signal, comprising:

• receiving a test signal;
• receiving a clock signal;
• generating delayed clock signals in response to the clock signal, wherein the delayed clock signals are offset from one another by less than one bit-cell time of the clock signal;
• identifying one of the delayed clock signals that is aligned with the test signal as an aligned clock signal by sequentially selecting the delayed clock signals with a multiplexer and sequentially comparing the selected delayed clock signals with the test signal;
• and
• providing another one of the delayed clock signals as the de-skewed clock signal in response to the aligned clock signal by selecting another one of the delayed clock signals with the multiplexer.

A method of providing a de-skewed clock signal, comprising:

• receiving a test signal;
• receiving a clock signal;
• generating delayed clock signals in response to the clock signal, wherein the delayed clock signals are offset from one another by less than one bit-cell time of the clock signal;
• identifying one of the delayed clock signals that is aligned with the test signal as an aligned clock signal by comparing inverted and non-inverted versions of the delayed clock signals to alternating bits of the test signal;
• and
• providing another one of the delayed clock signals as the de-skewed clock signal in response to the aligned clock signal.