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US 6,553,503 B1Granted
Circuitry, architecture and method(s) for synchronizing data
AssigneeCypress Semiconductor Corporation
InventorGabriel Li
Life of this patent
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Abstract
An apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a second programmable circuit configured to generate a second parallel data signal in response to (i) the first parallel data signal, (ii) the first control signal and (iii) a second control signal.
Claims20
A method for synchronizing data comprising the steps:
- (A) presenting (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals;
- and
- (B) generating a second parallel data signal in response to (i) said first parallel data signal, (ii) said first control signal and (iii) a second control signal comprising a local clock signal.
A method of storing data in one or more memory elements comprising the steps of:
- (A) writing data to one or more addresses in response to one or more first decoded control signals;
- and
- (B) presenting an output data signal in response to (i) said one or more addresses, (ii) a predetermined character encoded into a fixed address of said one or more addresses and (iii) one or more second decoded control signals.
The method according to 16, further comprising the step of:
- reading data from said one or more selected memory sections.
Dependencies are inferred from the claim text.