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US 6,553,488 B2Granted
Method and apparatus for branch prediction using first and second level branch prediction tables
AssigneeIntel Corporation
InventorsTse-Yu Yeh, Harshvardhan P. Sharangpani
Life of this patent
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Abstract
A branch predictor. A first branch prediction table is coupled to an instruction pointer generator to store tagged branch prediction entries and to provide branch predictions at high speed. A second branch prediction table is also coupled to the instruction pointer generator to store untagged branch prediction entries and to provide branch predictions for a much larger working set of branches, albeit at a slower speed.
Claims25
A processor comprising:
- a first branch prediction table (BPT), coupled to an instruction pointer (IP) generator, to store a first plurality of branch prediction entries;
- and
- a second BPT, coupled to the IP generator, to store a second plurality of branch prediction entries to predict both taken and not taken branches, wherein the processor does not include storage space for target address information associated with the second plurality of branch prediction entries.
A processor comprising:
- an instruction pointer (IP) generator;
- a first level branch prediction table (BPT), coupled to the IP generator, the first level BPT having stored therein a first plurality of branch prediction entries associated with a first plurality of addresses;
- a second level BPT, coupled to the IP generator, the second level BPT having stored therein a second plurality of branch prediction entries associated with a second plurality of addresses, wherein the second level BPT does not store target address information, and the second plurality of branch prediction entries are to predict both taken and not taken branches;
- and
- a decoder to determine the target address information.
2 more elements
A computer system comprising:
- program code including first and second branches that may be taken or not taken;
- and
- a processor including:
- a first branch predictor to store a first branch prediction entry and a first target address, both associated with the first branch;
- a second branch predictor to store a second branch prediction entry and to exclude a second target address, both associated with the second branch;
- and
- an instruction decoder to determine the second target address.
4 more elements
A processor comprising:
- a first branch predictor to store a first branch prediction entry and a first target address, both associated with a first branch that may be taken or not taken;
- a second branch predictor to store a second branch prediction entry and to exclude a second target address, both associated with a second branch that may be taken or not taken;
- and
- an instruction decoder to determine the second target address.
1 more element
Dependencies are inferred from the claim text.