Enhanced virtual renaming scheme and deadlock prevention therefor
AssigneeIntel Corporation
InventorsStephan J. Jourdan, Ronny Ronen, Michael Bekerman
Life of this patent
Estimating the term…
Abstract
In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated in a processor core.
Claims23
A register allocation unit, comprising:
- a value cache having a hit/miss output and a register ID output, comprising:
- an input for a new value signal,
- a plurality of cache entries, each to store values in association with a physical register ID, value portions of the cache entries including content addressable logic, and
- a controller, responsive to a match identified by the content addressable logic, to generate a HIT signal on the hit/miss output;
- and
- a free list having a register ID output, and
- a selector coupled to the register ID outputs of the value cache and the free list and having a control input coupled to the hit/miss output.
A register allocation unit, comprising:
- a value cache having a hit/miss output and a register ID output,
- a free list having a register ID output,
- a selector coupled to the register ID outputs of the value cache and the free list and having a control input coupled to the hit/miss output, and
- a register file having an addressing input coupled to the selector output.
A register allocation unit, comprising:
- a value cache having a hit/miss output and a register ID output,
- a free list having a register ID output,
- a selector coupled to the register ID outputs of the value cache and the free list and having a control input coupled to the hit/miss output, and
- a register file having an addressing input coupled to the free list output.
A register allocation unit for use in a processor core, comprising:
- a register file, populated by a plurality of physical entries, the physical entries each having a first portion to store data and a second portion to store a count of a number of logical registers that map to the respective physical registers,
- an instruction window queue to store information regarding active instructions, the information including an identifier of physical registers that store results of executed instructions therein,
- wherein, when an instruction is retired from the instruction window queue, the instruction window queue is to communicate a physical register identifier to the register file, and
- wherein, in response to the communication, the register file is to decrement the count stored in the identifier physical register.
A register allocation unit, comprising:
- a value cache having a hit/miss output and a register ID output,
- a free list having an empty indicator output and a register ID output,
- an instruction window queue having a register ID output,
- a first selector coupled to the register ID outputs of the free list and the instruction window queue, the first selector having a control input coupled to the empty indicator output, and
- a second selector coupled to the register ID output of the value cache and to an output of the first selector, the second selector having a control input coupled to the hit/miss output.
A method of allocating register in a processor core, comprising,
- when results from a newly executed instruction are received:
- determining whether the results match a value already stored in the core,
- on a match, assigning the instructions results to a register that stores the matching value, and
- when there is no match:
- determining whether any registers are available to store the results, and
- when no registers are available, storing the results in a register associated with a second instruction.
A method of allocating register in a processor core, comprising, when results from a newly executed instruction are received:
- determining whether the results match a value already stored in the core, and
- on a match, assigning the instructions results to a register that stores the matching value, wherein following the assigning, a plurality of logical registers, each generated from a different instruction, are mapped to the assigned register.
Dependencies are inferred from the claim text.