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US 6,553,482 B1Granted
Universal dependency vector/queue entry
AssigneeAdvanced Micro Devices, Inc.
InventorDavid B. Witt
Life of this patent
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Abstract
A processor employs an instruction queue and a dependency vector generation unit. The dependency vector generation unit generates a dependency vector for each instruction operation. Particularly, a dependency vector corresponding to a first instruction operation may be indicative of an ordering dependency between the first instruction operation and a prior instruction operation even if the first instruction operation does not have an operand dependency on the prior instruction operation. The instruction queue inhibits dependencies until each dependency within the dependency vector is satisfied.
Claims34
A processor comprising:
- a dependency vector generation unit configured to generate a dependency vector corresponding to a first instruction operation, wherein the dependency vector is indicative of an ordering dependency between the first instruction operation and a prior instruction operation if the first instruction operation is required to execute after the prior instruction operation independent of whether or not a result of the prior instruction operation is used during execution of the first instruction operation;
- and
- an instruction queue coupled to receive the dependency vector and the first instruction operation, wherein the instruction queue is configured to inhibit scheduling of the first instruction operation until each dependency indicated within the dependency vector is satisfied.
A method comprising:
- generating a dependency vector corresponding to a first instruction operation, the dependency vector indicating an ordering dependency between the first instruction operation and a prior instruction operation if the first instruction operation is required to execute after the prior instruction operation independent of whether or not a result of the prior instruction operation is used during execution of the first instruction operation;
- storing the dependency vector and the first instruction operation in an instruction queue;
- satisfying the ordering dependency;
- and
- scheduling the first instruction operation responsive to the satisfying.
2 more elements
A computer system comprising:
- a processor including:
- a dependency vector generation unit configured to generate a dependency vector corresponding to a first instruction operation, wherein the dependency vector is indicative of an ordering dependency between the first instruction operation and a prior instruction operation if the first instruction operation is required to execute after the prior instruction operation independent of whether or not a result of the prior instruction operation is used during execution of the first instruction operation;
- and
- an instruction queue coupled to receive the dependency vector and the first instruction operation, wherein the instruction queue is configured to inhibit scheduling of the first instruction operation until each dependency indicated within the dependency vector is satisfied;
- and
- a peripheral device for communicating between the computer system and another computer system.
3 more elements
A processor comprising:
- a dependency vector generation unit configured to generate a dependency vector corresponding to a first instruction operation, wherein the dependency vector is indicative of an ordering dependency between the first instruction operation and a prior instruction operation if the prior instruction operation is a store address instruction operation and the first instruction operation is a load instruction operation even if the first instruction operation does not have an operand dependency on the prior instruction operation, wherein the store address instruction operation is defined to generate an address of a store but not supply the data of the store;
- and
- an instruction queue coupled to receive the dependency vector and the first instruction operation, wherein the instruction queue is configured to inhibit scheduling of the first instruction operation until each dependency indicated within the dependency vector is satisfied.
A processor comprising:
- a dependency vector generation unit configured to generate a dependency vector corresponding to a first instruction operation, wherein the dependency vector is indicative of a store-load forward dependency between the first instruction operation and a prior instruction operation if the store-load forward dependency is predicted even if the first instruction operation does not have an operand dependency on the prior instruction operation;
- and
- an instruction queue coupled to receive the dependency vector and the first instruction operation, wherein the instruction queue is configured to inhibit scheduling of the first instruction operation until each dependency indicated within the dependency vector is satisfied.
A processor comprising:
- a dependency vector generation unit configured to generate a dependency vector corresponding to a first instruction operation, wherein the dependency vector is indicative of an ordering dependency between the first instruction operation and a prior instruction operation if the first instruction operation is a synchronizing instruction operation, regardless of a type of the prior instruction operation, even if the first instruction operation does not have an operand dependency on the prior instruction operation;
- and
- an instruction queue coupled to receive the dependency vector and the first instruction operation, wherein the instruction queue is configured to inhibit scheduling of the first instruction operation until each dependency indicated within the dependency vector is satisfied.
A processor comprising:
- a dependency vector generation unit configured to generate a dependency vector corresponding to a first instruction operation, wherein the dependency vector is indicative of an ordering dependency between the first instruction operation and a prior instruction operation if the prior instruction operation is a synchronizing instruction operation, regardless of a type of the first instruction operation, even if the first instruction operation does not have an operand dependency on the prior instruction operation;
- and
- an instruction queue coupled to receive the dependency vector and the first instruction operation, wherein the instruction queue is configured to inhibit scheduling of the first instruction operation until each dependency indicated within the dependency vector is satisfied.
Dependencies are inferred from the claim text.