Computer memory access
AssigneeSTMicroelectronics S.r.l.
InventorNicolas Grossier
Life of this patent
Estimating the term…
Abstract
A memory for a computer system that includes a plurality of memory banks which provide an interleaved memory region as well as X and Y memory regions. Each memory access address includes a most significant set of bits indicating which of the interleaved, X, or Y memory regions is to be accessed. Each memory access address also includes a least significant set of bits indicating an address within the bank of the access region. At least one bit in the least significant set is a bank selector and one bit of the most significant set of bits is an X or Y region selector.
Claims10
Memory circuitry for a computer system, comprising:
- a plurality of memory banks forming at least part of a mapped memory space of the computer system,
- a first part of said memory space providing an interleaved memory region formed by each of said plurality of memory banks so that data is stored in each of said plurality of memory banks within said interleaved memory region,
- a second part of said memory space providing an X memory region using at least one of said plurality of memory banks, and
- a third part of said memory space providing a Y memory region using each memory bank of said plurality of memory banks not used in said X memory region,
- wherein each of said interleaved memory region, said X memory region and said Y memory region are separately mapped within said memory space;
- circuitry to generate an access address and an indication of whether a memory access is an interleaved access or an X or Y access, wherein said access address includes a most significant set of bits which indicate which of said interleaved memory region, said X memory region or said Y memory region is to be accessed, and a least significant set of bits which include an indication of an address within a memory bank of the accessed memory region, at least one bit within said least significant set of bits selecting one memory bank within an accessed memory region if the accessed memory region has more than the one memory bank, and one bit within said most significant set of bits indicating selectively said X memory region or said Y memory region during the X or Y access;
- and
- memory access circuitry arranged to selectively access said memory space in response to said access address.
A method of accessing memory in a computer system comprising:
- defining a plurality of memory banks forming at least part of a mapped memory space, a first part of said memory space providing an interleaved memory region formed by each of said plurality of memory banks so that data is stored in each of said plurality of memory banks within the interleaved region, a second part of said memory space providing an X memory region using only one or some of said plurality of memory banks, and a third part of said memory space providing a Y memory region using each memory bank not used in the X memory region, each of the interleaved, X and Y memory regions being separately mapped within said memory space;
- generating an access address including a most significant set of bits which indicates which of the interleaved memory region, X memory region or Y memory region is to be accessed, and a least significant set of bits which includes an indication of an address within a memory bank of an accessed region, at least one of said least significant set of bits selecting one memory bank within the accessed region if the accessed region has more than one memory bank, and one of said most significant set of bits indicating selectively the X memory region or Y memory region during an X or Y access;
- and
- accessing selectively said memory space in response to said access address.
Dependencies are inferred from the claim text.