Microprocessor and address translation method for microprocessor

A method for implementing dynamic address translation from a virtual address to a physical address in a microprocessor, comprising the steps of:

• preparing an address translation buffer consisting of a lower-level buffer having no entry lock function and a higher-level buffer having an entry lock function and having higher associativity than the associativity of said lower-level buffer;
• preparing in a main memory an address translation table for storing address translation for each page, said address translation table having a data structure containing a specifier to indicate whether or not a corresponding address translation is to be locked in said address translation buffer;
• and
• locking an entry in said higher-level buffer in accordance with said lock specifier contained in said data structure of said address translation table.

A computer incorporating a microprocessor equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis, said address translation mechanism comprising:

• (a) an address translation buffer having an entry lock function and including:
• (1) a lower-level buffer organized as a lower-level hierarchy of said address translation buffer and having no entry lock function, and
• (2) a higher-level buffer organized as a higher-level hierarchy of said address translation buffer and having said entry lock function, said higher-level buffer having higher associativity than the associativity of said lower-level buffer;
• and
• (b) control logic for controlling operation of said address translation buffer.