Byte-wise tracking on write allocate
AssigneeIP-First, LLC
InventorsDarius D. Gaskins, Rodney E. Hooker
Life of this patent
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AssigneeIP-First, LLC
InventorsDarius D. Gaskins, Rodney E. Hooker
Estimating the term…
An apparatus and method within a pipeline microprocessor are provided for allocating a cache line within an internal data cache upon a write miss to the data cache. The that apparatus and method allow data to be written to the allocated cache line before fill data for the allocated cache line is received from external memory over a system bus. The apparatus includes write allocate logic and a write buffer. The write allocate logic allocates the cache line within the data cache, it stores data corresponding to the write miss within the allocated cache line, and queues a speculative write command directing an external bus to store said the data to the external memory in the event that transfer of the fill data is interrupted. The speculative write command is stored in the write buffer and, in the event of an interruption such as a bus snoop to the allocated cache line, the write buffer issues the speculative write command to the system bus, thereby writing the data to external memory. When the fill data is received from the system bus, it is filtered by byte-wise tracking logic such that only bytes positions which have not been written during the interim are updated in the allocated cache line.
An apparatus in a pipeline microprocessor for allocating a first cache line within a data cache upon a write to an external memory location that is not presently within the data cache, the apparatus comprising:
The apparatus as recited in 4, further comprising:
The apparatus as recited in 8, further comprising:
A cache line allocation apparatus within a pipeline microprocessor, for allocating a selected cache line upon a write miss, the cache line allocation apparatus comprising:
The cache line allocation apparatus as recited in 15, further comprising:
An apparatus for performing write allocation in a data cache when a write miss occurs, the apparatus comprising:
The apparatus as recited in 19, wherein said write allocate logic further comprises:
The apparatus as recited in 21, further comprising:
A method for allocating a cache line within a pipeline microprocessor, the method comprising:
Dependencies are inferred from the claim text.