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US 6,553,467 B1Granted
Bank information pre-decode apparatus
AssigneeIntel Corporation
InventorJames M. Ottinger
Life of this patent
Estimating the term…
Abstract
An apparatus for accelerating the speed of memory access cycles in a multi-bank memory. The apparatus includes decode logic that pre-decodes bank information from a requested address signal while the corresponding request is queued in the request queue. The pre-decode logic is propagated to the memory controller, preferably by re-insertion into the request queue, to facilitate more rapid memory accesses.
Claims12
An apparatus comprising:
- an address bus;
- a memory access request queue coupled to said address bus;
- a multi-bank memory and associated memory control logic coupled to said request queue;
- and
- decode logic coupled between said address bus and said memory to pre-decode bank information from an address from said address bus, said bank information having a bit for each bank in said memory having one bit corresponding to the bank of said address set to a first state and the remaining bits of the bank information being set to a second state, wherein said bank information is propagated through said request queue to said memory. said bank information being propagated from said decode logic to a corresponding request in said request queue.
2 more elements
An apparatus comprising:
- an address bus;
- a memory access request queue coupled to said address bus;
- decode logic coupled to said address bus and said request queue to pre-decode bank information from an address received from said address bus and to propagate said bank information to a corresponding request in said request queue, said bank information having a bit for each bank in said memory having one bit corresponding to the bank of said address set to a first state and the remaining bits of the bank information being set to a second state.
An apparatus comprising:
- a request queue to store plurality of entries, said queue having a beginning and an end;
- an address bus coupled to said request queue;
- logic coupled to at least a portion of said address bus to receive an address therefrom and to pre-decode bank select information from said address said logic to insert said bank select information in a corresponding request propagates from the beginning to the end of said queue, said bank information having a bit for each bank in said memory having one bit corresponding to the bank of said address set to a first state and the remaining bits of the bank information being set to a second state.
Dependencies are inferred from the claim text.