Microprocessor having improved memory management unit and cache memory

Abstract

Methods of managing a cache memory system in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in a memory space. The entries of the cache memory are in locations in a register space separate from the memory space. A first instruction that operates only on locations in a register space but not on locations in memory space may be executed to obtain address information from at least one entry of the cache memory. The obtained address information be compared with target address information. If the comparison between the obtained address information and the target address information results in a correspondence, then a first operation may be performed on the entry of the cache memory. If the comparison between the obtained address information and the target address information does not result in a correspondence, then the fit first operations not performed on the entry of the cache memory. Management operations may thus be performed on the cache memory without using locations in memory space. The first operation may include invalidate, flush or purge operations. The cache memory may be a virtual cache memory that has a plurality of entries each including physical address information and logical address information. The obtained address information, may be logical address information or physical address information. The first instruction may be a GET instruction for reading information from entries of the translation lookaside buffer or the cache memory. The second instruction may be a PUT instruction for writing information to entries of the translation lookaside buffer or the cache memory.

Dependencies are inferred from the claim text.