Memory command converter and application system
AssigneeLeadtek Research Inc.
InventorsKun-Ho Wu, Hai-Feng Chuang
Life of this patent
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Abstract
A memory command converter and its application system. The memory command converter serves as a command translator between an extended data output dynamic random access memory (EDO DRAM) and a synchronous dynamic random access memory (SDRAM) so that an application system for using EDO DRAM may also use mainstream SDRAM through the converter.
Claims11
An application system for memory command conversion, comprising:
- a control chip for outputting a first command control signal to control an extended data output dynamic random access memory (EDO DRAM);
- a synchronous dynamic random access memory (SDRAM) chip for holding application system data;
- a memory command converter coupled to the control chip and the SDRAM chip for receiving the first command control signal from the control chip and for converting the first command control signal into a second command control signal acceptable by the SDRAM chip;
- and
- a clocking generator coupled to the memory command converter for providing necessary clocking signals to the memory command converter.
A memory command converter for converting a first command control signal from a control chip for controlling an extended data output dynamic random access memory (EDO DRAM) into a second command control signal acceptable to a synchronous dynamic random access memory (SDRAM) chip, comprising:
- a mode control selection storage device coupled to the control chip for receiving and holding a mode control selection value of the SDRAM chip;
- a command control circuit coupled to the mode control selection storage unit, the control chip and the SDRAM chip for setting the operating mode of the SDRAM and converting the first command control signal into the second command control signal according to the mode control selection value within the mode control selection storage device;
- and
- a clocking control circuit coupled to an external clocking generator, the command control circuit, the control chip and the SDRAM chip for receiving a clocking signal from the clocking generator, converting the clocking signal and dispatching the converted signal to the command control circuit, the control chip and the SDRAM chip to serve as a synchronizing pulse.
Dependencies are inferred from the claim text.