US 6,553,449 B1 · System and method for providing concurrent row and column commands

Abstract

A system and method for providing concurrent column and row operations in a memory system is provided. The memory system includes a memory controller, a plurality of memory devices, and communication paths between the memory controller and the plurality of memory devices. The memory controller is coupled to each memory device through a communication path that provides a column chip select signal to the memory device and a communication path that provides a row chip select signal to the memory device. The dual chip select signals allow a column operation to be carried out in the memory device simultaneously with a row operation in the memory device. The communication paths further include a column command communication path that provides column commands to the memory devices, a column address communication path that provides column addresses for the column commands to the memory devices, a row command communication path that provides row commands to the memory devices, and a row address communication path that provides row addresses for the row commands to the memory device.

Claims18

Dependent claims

A memory system, comprising:

a memory controller that sends data and signals to at least one memory device and receives data and signals from the at least one memory device;
an external buffer interconnecting the memory controller and the at least one memory device to transfer data and signals between the memory controller and the at least one memory device;
a first selecting communication path that provides a first selecting signal to the at least one memory device for selection to carry out a column command;
and
a second selecting communication path that provides a second selecting signal to the at least one memory device for selection to simultaneously carry out a row command with the column operation.

2 more elements

A method of providing concurrent row and column commands in a memory system including a memory controller and at least one memory device having a memory cell array, the method comprising:

selecting the at least one memory device for carrying out a column operation in the memory cell array;
selecting the at least one memory device for simultaneously carrying out a row operation in the memory cell array With the column operation;
providing column commands for the column operation to the at least one memory device through an external buffer interconnecting the memory controller and the at least one memory device;
providing column addresses for the column commands to the at least one memory device through the external buffer interconnecting the memory controller and the at least one memory device;
providing row commands for the row operation to the at least one memory device through the external buffer interconnecting the memory controller and the at least one memory device;
and
providing row addresses for the row commands to the at least one memory device through the external buffer interconnecting the memory controller and the at least one memory device.

4 more elements

A computer readable medium for use in conjunction with a memory system including a memory controller and at least one memory device having a memory cell array, the computer readable medium including computer readable instructions encoded thereon for:

selecting the at least one memory device for carrying out a column operation in the memory cell array;
selecting the at least one memory device for simultaneously carrying out a row operation in the memory cell array with the column operation;
providing column commands for the column operation. to the at least one memory device through an external buffer interconnecting the memory controller and the at least one memory device;
providing column addresses for the column commands to the at least one memory device through the external buffer interconnecting the memory controller and the at least one memory device;
providing row commands for the row operation to the at least one memory device through the external buffer interconnecting the memory controller and the at least one memory device;
and
providing row addresses for the row commands to the at least one memory device through the external buffer interconnecting the memory controller and the at least one memory device.

4 more elements

Dependencies are inferred from the claim text.

System and method for providing concurrent row and column commands

Life of this patent

System and method for providing concurrent row and column commands

Life of this patent

Abstract

Claims18