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US 6,553,446 B1Granted
Modular input/output controller capable of routing packets over busses operating at different speeds
AssigneeSilicon Graphics, Inc.
InventorSteven Miller
Life of this patent
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Abstract
A modular, scalable high-bandwidth computer architecture. A single integrated router/bridge ASIC defines a family of peripheral controllers that accept high-speed packet switched data, either for routing to other, identical controllers, or for routing to on-board PCI buses, or a combination of the two destinations, depending on the number of ASICs employed and their selectable configuration.
Claims8
A bi-modal peripheral controller for a computer system, comprising:
- a) at least two high-speed buses;
- b) at least one low-speed bus;
- c) a packet switched router of data from a first of the high-speed or low-speed buses to a second of the high-speed or low-speed buses, comprising a plurality of communication paths permitting simultaneous multiple communications between any of the high-speed or low-speed buses;
- d) a bridge coupled between the router and each low-speed bus;
- e) a plurality of write buffers, coupled to each bridge, which couple a plurality of write transactions on the low-speed bus coupled to that bridge into a cache line sized transfer to the router;
- f) a plurality of read buffers, coupled to each bridge, in which each read buffer stores fetched data according to a read request from a device connected to the low-speed bus coupled to that bridge so that the device can access the read buffers multiple times to retrieve the data;
- g) a prefetcher, coupled to each bridge, which reads sequential cache lines until the read buffers are full, a page boundary is encountered, or the read buffers are caused to be flushed, if the device connected to the low-speed device coupled to that bridge generates a read request and there is no corresponding data contained in the read buffers;
- and
- h) means for selecting between first and second modes, in which the first mode permits the router to connect any high-speed bus to any other bus, and the second mode permits the router to connect high-speed buses only to low-speed buses.
6 more elements
In a computer system, at least one bi-modal peripheral controller comprising:
- a) at least two high-speed buses;
- b) at least one low-speed bus;
- c) a router of data packets, using routing information obtained from the data packets to route the data packets from a first of the high-speed or low-speed buses to a second of the high-speed or low-speed buses;
- d) means for compensating for memory latency between the low-speed bus and either high-speed bus;
- and
- e) means for selecting between first and second modes, such that the first mode permits the router to connect any high-speed bus to any other bus, and the second mode permits the router to connect high-speed buses only to low-speed buses.
3 more elements
In a computer system, at least one bi-modal peripheral controller comprising:
- a) at least two high-speed buses;
- b) at least one low-speed bus;
- c) means for routing packet switched data from a first of the high-speed or low-speed buses to a second of the high-speed or low-speed buses;
- d) means for compensating for memory latency between the low-speed bus and either high-speed bus;
- e) means for selecting between first and second modes, such that the first mode permits the routing means to connect any high-speed bus to any other bus, and the second mode permits the routing means to connect high-speed buses only to low-speed buses;
- and
- in which at least one of the high-speed buses employs differential signaling and at least another of the high speed buses does not.
4 more elements
A peripheral controller for a computer system, comprising:
- a) a plurality of bi-modal ASICs,
- b) at least two high-speed buses;
- c) at least one low-speed bus;
- d) a packet switched data router configured to route data packets from a first of the high-speed or low-speed buses to a second of the high-speed or low-speed buses;
- e) means for compensating for memory latency between the low-speed bus and either high-speed bus;
- and
- in which one ASIC is in a mode that permits the router to connect any high-speed bus to any other but using routing information obtained from the data packets, and all other ASICs are in a mode that permits the router to connect high-speed buses only to low-speed buses using information obtained from the data packets.
4 more elements
A peripheral controller for a computer system, comprising:
- a) a plurality of three identical bi-modal ASICs,
- b) at least two high-speed buses;
- c) at least one low-speed bus;
- d) means for routing packet switched data from a first of the high-speed or low-speed buses to a second of the high-speed or low-speed buses;
- e) means for compensating for memory latency between the low-speed bus and either high-speed bus;
- in which one ASIC is in a mode that permits the routing means to connect any high-speed bus to any other bus, and all other ASICs are in a mode that permits the routing means to connect high-speed buses only to low-speed buses.
3 more elements
A peripheral controller for a computer system, comprising:
- a) a plurality of bi-modal ASICs,
- b) at least two high-speed buses;
- c) at least one low-speed bus;
- d) means for routing packet switched data from a first of the high-speed or low-speed buses to a second of the high-speed or low-speed buses;
- c) means for compensating for memory latency between the low-speed bus and either high-speed bus;
- in which one ASIC is in a mode that permits the routing means to connect any high-speed bus to any other bus, and all other ASICs are in a mode that permits the routing means to connect high-speed buses only to low-speed buses;
- and
- in which at least one of the high-speed buses employs differential signaling and at least another of the high speed buses does not.
5 more elements
Dependencies are inferred from the claim text.