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US 6,553,445 B1Granted
Method and apparatus for reducing noise associated with switched outputs
AssigneeATI International SRL
InventorsOleg Drapkin, Grigori Temkine
Life of this patent
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Abstract
A method and apparatus for simultaneously communicating data over a plurality of data links, such as a bus, determines initial logic levels of data to the output on each of the plurality of data links and changes the logic levels, such as inverting the data, of at least some of the data to produce logic level adjusted data in response to determining the initial logic level of the data to reduce switching transitions of simultaneously switched output data over the plurality of data links.
Claims32
A method for simultaneously communicating data over a plurality of data links comprising the steps of:
- determining initial logic levels of data to be output on each of the plurality of data links;
- and
- changing the logic levels of at least some of the data to produce logic level adjusted data in response to determining the initial logic level of the data without comparing the initial logic level to previously sent data, to reduce a number of switching transitions associated with simultaneously outputting data over the plurality of data links.
An apparatus for simultaneously outputting data over a plurality of data links comprising:
- a data preprocessing circuit, operatively coupleable to at least one initial data provider having a plurality of parallel data outputs associated with a plurality of corresponding first data links, the data preprocessing circuit having a plurality of parallel inputs operatively coupleable to the plurality of parallel data outputs, wherein the data preprocessing circuit is operative to change logic levels of at least some of the data from the parallel outputs to produce logic level adjusted data in response to determining the initial logic level of the data without comparing the initial logic level to previously sent data, reduce a number of switching transitions associated with simultaneously outputting data over the plurality of data links.
A data pre-processing circuit comprising:
- a plurality of first parallel inputs;
- a plurality of first parallel simultaneous switchable outputs (SSO);
- a logic level changing circuitry operative to change logic levels of at least some of parallel data received via the plurality of first parallel inputs to produce logic level adjusted data that is output via the plurality of SSO, in response to determining an initial logic level of data without comparing the initial logic level to previously sent data, received via the plurality of first parallel inputs;
- and
- logic level adjustment code bit generating logic operative to generate at least one logic level adjustment code bit and to output the at least one logic level adjustment code bit associated with simultaneously communicated logic level adjusted data that is output via the plurality of first SSO.
2 more elements
A data pre-processing circuit comprising:
- a plurality of parallel inputs;
- a plurality of parallel simultaneous switchable outputs (SSO);
- and
- logic level re-adjustment circuitry operative to change logic levels of at least some of parallel data received via the plurality of parallel inputs without comparing the initial logic level to previously sent data, to produce initial logic level data that is output via the plurality of SSO, in response to at least one logic level adjustment code bit received via the at least one logic level adjustment code bit input port.
1 more element
A data communication system comprising:
- a data transmitting circuit including a data provider having simultaneous switching outputs;
- a data receiving circuit including a data receiver having parallel input ports;
- and
- a data preprocessing circuit, operatively interposed between the data transmitting circuit and the data receiving circuit via a data bus, having:
- (a) a transmitting preprocessing circuit that includes:
- a first plurality of parallel inputs;
- a first plurality of parallel simultaneous switchable outputs (SSO);
- at least one logic level adjustment code bit output port;
- logic level changing circuitry operative to change logic levels of at least some of parallel data received via the plurality of first parallel inputs to produce logic level adjusted data that is output via the plurality of first SSO, in response to determining an initial logic level of data received without comparing the initial logic level to previously sent data, and includes logic level adjustment code bit generating logic operative to generate at least one logic level adjustment code bit and to output the at least one logic level adjustment code bit associated with simultaneously communicated logic level adjusted data that is output via the plurality of first SSO;
- and
- (b) a receiving preprocessing circuit that includes:
- a plurality of second parallel inputs;
- a plurality of second parallel simultaneous switchable outputs (SSO);
- at least one logic level adjustment code bit input port;
- and
- logic level re-adjustment circuitry operative to change logic levels of at least some of parallel data received via the plurality of second parallel inputs to produce initial logic level data that is output via the plurality of second SSO, in response to at least one logic level adjustment code bit received via the at least one logic level adjustment code bit input port.
13 more elements
Dependencies are inferred from the claim text.