Computer system implementing flush operation

Abstract

A computer system is presented which implements a “flush” operation providing a response to a source which signifies that all posted write operations previously issued by the source have been properly ordered within their targets with respect to other pending operations. The computer system includes multiple processing nodes within a processing subsystem and at least one input/output (I/O) node coupled to a processing node including a host bridge. The host bridge receives non-coherent posted write commands from the I/O node and responsively generates corresponding coherent posted write commands within the processing subsystem. Each posted write command has a target within the processing subsystem. The host bridge includes a data buffer for storing data used to track the status of non-coherent posted write commands. The I/O node issues a flush command to ensure that all previously issued non-coherent posted write commands have at least reached points of coherency within the processing subsystem. The host bridge issues a non-coherent target done response to the I/O node in response to: (i) the flush command, and (ii) coherent target done responses received from all targets of posted write commands previously issued by the I/O node. Coherent target done responses signify write commands have at least reached points of coherency within the processing subsystem. The non-coherent target done response signals the I/O node that all non-coherent posted write commands previously issued by the I/O node have at least reached points of coherency within the processing subsystem.

Dependencies are inferred from the claim text.