Reconfigurable processor devices

A method of constructing a central processing unit from a reconfigurable device, the reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices;

• and means to define a configuration of the connection matrix, the method comprising:
• allocating one or more of the processing devices to form an arithmetic logic unit of the central processing unit, wherein each of the processing devices comprises an arithmetic logic unit adapted to perform a function on input operands and produce an output, and wherein said input operands are provided as inputs to the arithmetic logic unit from the interconnect on the same route in each cycle;
• associating a first memory, as a register file, with the arithmetic logic unit of the central processing unit;
• and
• associating a second memory, as a code memory, with the arithmetic logic unit of the central processing unit, to provide instructions for the central processing unit, wherein instruction inputs for the arithmetic logic unit of the central processing unit are provided from the second memory;
• wherein either or both of the first memory and the second memory are provided by reconfiguration of one or more processing devices into memory available for use by the central processing unit configured onto the reconfigurable device.