Timing optimization in presence of interconnect delays

A method of buffering a long wire comprising:

• using a computer to receive an electronic representation of a circuit including a long wire, the long wire having resistance and capacitance per unit length of Rw and Cw, respectively, and a length of L;
• using a computer to determine a size wopt of buffers to be used to buffer the long wire, to be w opt = τ ⁢ ⁢ C w R w ⁢ C 0 2
• where τ is the intrinsic delay of an ideal inverter and C0 is the input capacitance of a minimum size buffer;
• and
• using the computer to modify the electronic representation based on wopt.

A method of buffering a long wire comprising:

• using a computer to receive an electronic representation of a circuit including a long wire, the long wire having resistance and capacitance per unit length of Rw and Cw, respectively, and a length of L;
• using the computer to determine a spacing Lkopt between buffers to be used to buffer the long wire, each of the buffers having an intrinsic delay of pb, to be L kopt = 2 ⁢ τ ⁢ ( 1 + p b ) R w ⁢ C w
• where τ is the intrinsic delay of an ideal inverter;
• and
• using the computer to modify the electronic representation based on Lkopt.

A method of calculating delay in a long wire comprising:

• using a computer to receive an electronic representation of a circuit including a long wire, the long wire having resistance and capacitance per unit length of Rw and Cw, respectively, and a length of L;
• and
• using the computer to determine a delay Dk of the long wire when a length of the long wire is less than an optimal spacing of buffers in the long wire, to be D k = τ ⁢ ⁢ ( 1 + C w ⁢ L C b + p b ) + R b ⁢ C w ⁢ L + R w ⁢ C b ⁢ L + R w ⁢ C w ⁢ L 2 2
• where Rb and Cb are resistance and capacitance, respectively, of buffers later used to buffer the long wire;
• pb an intrinsic delay of the buffers;
• and τ the intrinsic delay of an ideal inverter.

A method of calculating delay in a long wire comprising:

• using a computer to receive al electronic representation of a circuit including a long wire, the long wire having resistance and capacitance per unit length of Rw and Cw, respectively, and a length of L;
• using the computer to determine a delay Dk of the long wire when a length of the long wire is greater than an optimal spacing of buffers in the long wire, to be
• Dk=L{square root over (RwCw)}({square root over (2τ(1+pb))}+2C0{square root over (τ)})
• where pb is an intrinsic delay of the buffers and τ the intrinsic delay of an ideal inverter.