System for mapping logical functional test data of logical integrated circuits to physical representation using pruned diagnostic list
AssigneeTexas Instruments Incorporated
InventorHari Balachandran
Life of this patent
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Abstract
An improved method for mapping logical function test data of logical integrated circuits to physical representations uses a pruned diagnostic list. The steps include creating a final logical diagnostic list of potential bridging faults in response to testing the circuit for stuck-at faults at a plurality of nets of the circuit, receiving the physical data associated with nets of the circuit, applying adjacency criteria to the physical data, generating a pruned diagnostic list of potential bridging faults in response to applying the adjacency criteria, performing in-line inspection to obtain second localized probable defect data and correlating second localized portable defect data with the pruned diagnostic list.
Claims10
A method of automated defect localization in the testing of semiconductor integrated circuits, comprising the steps of:
- creating a final logical diagnostic list of potential bridging faults in response to testing the circuit for stuck-at faults at a plurality of nets of the circuit, each potential bridging fault being associated with at least two tested nets of the circuit;
- receiving physical data associated with each of the tested nets of the circuit;
- applying adjacency criteria to the physical data associated with the at least two tested nets that are associated with each of the listed potential bridging faults;
- generating the pruned diagnostic list of potential bridging faults in response to applying the adjacency criteria;
- performing in-line inspection of the integrated circuits to obtain second localized probable defect data;
- and
- correlating the pruned diagnostic list of potential bridging faults with said second localized probable defect data.
Dependencies are inferred from the claim text.