Fractional-N frequency synthesizer with fractional compensation method

A fractional-N frequency synthesizer for a mobile terminal, comprising:

• a phase detector circuit that comprises,
• a first phase detector having a first input port coupled to receive a reference signal, a second input port, a third input port and an output port, and
• a second phase detector having a first input port coupled to receive the reference signal, a second input port, a third input port and an output port;
• a loop filter having a first input port coupled to the output ports of the first and second phase detectors and an output port;
• a voltage-controlled oscillator having an input port coupled to the output port of the loop filter and transmitting a prescribed frequency signal at an output port;
• a programmable modulus divider having a first output port coupled to the second input port of the first phase detector to transmit a first divided signal, a second output port coupled to the second input port of the second phase detector to transmit a second divided signal, a first input port coupled to the output port of the voltage-controlled oscillator and a second input port;
• and
• an accumulator having a first output port coupled to the second input port of the programmable modulus divider and a second output port coupled to the third input ports of the phase detectors.

A method for generating frequency signals, comprising:

• (a) dividing a frequency signal output from an oscillator by a first value to produce a first divided signal;
• (b) dividing a frequency signal output from an oscillator by a second value to produce a second divided signal;
• (c) comparing the first divided signal to a reference signal to generate a first control signal;
• (d) comparing the second divided signal to said reference signal to generate a second control signal;
• and
• (e) adjusting the oscillator based on the first control signal and second control signal.

A phase-locked-loop, comprising:

• an oscillator;
• a divider which divides a frequency signal output from the oscillator by a first value to produce a first divided signal and by a second value to produce a second divided signal;
• a first phase detector which compares the first divided signal to a reference signal to generate a first control signal for adjusting the oscillator;
• and
• a second phase detector which compares the second divided signal to said reference signal to generate a second control signal for adjusting the oscillator.