Circuit and method for linear control of a spread spectrum transition
AssigneeCypress Semiconductor Corporation
InventorsI-Teh Sha, Albert Chen, Kuang-Yu Chen
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Abstract
A spread spectrum clock generator comprising a spread spectrum modulation circuit and a control circuit. The spread spectrum modulation circuit may be configured to generate a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The control circuit may be configured to synchronize the command signal to a feedback signal. The sequence of linearity ROM codes and the sequence of spread spectrum ROM codes may be generated by predetermined mathematical formulas and optimized in accordance with predetermined criteria.
Claims20
A spread spectrum clock generator comprising:
- a spread spectrum modulation circuit configured to generate a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal;
- and
- a control circuit configured to synchronize said command signal to a feedback signal, wherein said sequence of linearity ROM codes and said sequence of spread spectrum ROM codes are generated according to one or more predetermined mathematical formulas and optimized in accordance with predetermined criteria.
A spread spectrum clock generator comprising:
- means for generating a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal;
- and
- means for synchronizing said command signal to a feedback signal, wherein said sequence of linearity ROM codes and said sequence of spread spectrum ROM codes are generated according to one or more predetermined mathematical formulas and optimized in accordance with predetermined criteria.
A method of producing a low slew rate linear transition in the turn-on transient response of a spread spectrum clock generator comprising the steps of:
- (A) generating a sequence of linearity ROM codes according to a predetermined mathematical formula;
- (B) optimizing said sequence of linearity ROM codes according to one or more predetermined criteria;
- and
- (C) modulating a clock signal in response to (i) said sequence of linearity ROM codes and (ii) a command signal.
Dependencies are inferred from the claim text.