Semiconductor memory device operable for both of CAS latencies of one and more than one
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTadaaki Yamauchi, Junko Matsumoto, Takeo Okamoto
Life of this patent
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Abstract
A repeater circuit, operative in response to a clock signal transmitted from an internal clock generation circuit on a clock signal line, outputs one of first and second clock signals depending on whether a CAS latency of one or that of two is applied. The first clock signal pulses twice for activation within the period of an external clock. An input/output circuit, for the CAS latency of no less than two, stores read data in response to the second clock signal attaining the active state, and for the CAS latency of one, stores read data in response to the first clock signal and an equalization signal each attaining the active state.
Claims8
A semiconductor memory device synchronized with an external clock signal to input a command and input and output data, comprising:
- a control circuit controlling an operation of said semiconductor memory device;
- a memory cell array including a plurality of memory cells arranged in rows and columns;
- an internal clock circuit operative in response to said external clock signal to generate an internal clock signal;
- a clock signal line transmitting said internal clock signal;
- a clock conversion circuit receiving said internal clock signal on said clock signal line and selectively outputting one of first and second clock signals based on said internal clock signal depending on which one of first and second modes of operation is designated, said first mode of operation allowing starting reading data from said memory cell array one clock after a read command is applied when said external clock signal has a first transition for activation, said second mode of operation allowing starting reading data from said memory cell array two clocks after said read command is applied when said external clock signal has said first transition for activation, said second clock signal in said second mode of operation being equal in frequency to said external clock and being synchronized with said external clock, said first clock signal in first mode of operation pulsing twice for activation within a period of said internal clock signal;
- a data bus transmitting data read from said memory cell array;
- an equalization circuit operative in response to an equalization signal to equalize said data bus;
- a command signal line transmitting said equalization signal from said control circuit;
- a data input/output terminal;
- and
- an input/output circuit outputting to said data input/output terminal the read data transmitted on said data bus, said input/output circuit including a latch circuit operative in said second mode of operation to store and hold said read data therein in response to said second clock signal attaining an active state, and operative in said first mode of operation to store and hold said read data therein in response to said first clock signal and said equalization signal each attaining an active state.
Dependencies are inferred from the claim text.