Semiconductor memory device and non-volatile semiconductor memory device provided with a plurality of internal counters

A semiconductor memory device having a first operation mode operable with a first cycle and a second operation mode operable with a second cycle that is longer than the first cycle, the semiconductor memory device comprising:

• a first address counter that generates addresses in serial order subsequent to a first reference address inputted from an external section by first cycle generated in synchronous with a clock signal supplied from the external section with the first operation mode;
• and
• a second address counter that generates addresses in serial order subsequent to a second reference address inputted from the external section by second cycle generated asynchronous with a clock signal supplied from the external section with the second operation mode.

A non-volatile semiconductor memory device having readout mode operable with first cycle and write mode or erase mode operable with second cycle that is longer than the first cycle, the non-volatile semiconductor memory device comprising:

• a first address counter that generates addresses in serial order subsequent to a first reference address inputted by an external section by the first cycle generated in synchronous with a clock signal supplied from the external section with the readout mode;
• and
• a second address counter that generates addresses in serial order subsequent to a second reference address inputted by the external section by the second cycle generated in synchronous with a clock signal supplied from the external section with either the write mode or the erase mode.

A non-volatile semiconductor memory device having readout mode operable with first cycle and write mode or erase mode operable with second cycle that is longer than the first cycle, the non-volatile semiconductor memory device comprising:

• a first address counter that generates addresses in serial order subsequent to a first reference address inputted from an external section by the first cycle generated in synchronous with a clock signal supplied from the external section with the readout mode;
• and
• a second address counter that generates addresses in serial order subsequent to a second reference address inputted from the external section by the second cycle generated in asynchronous with a clock signal supplied from the external section with either the write mode or the erase mode.