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US 6,552,955 B1Granted
Semiconductor memory device with reduced power consumption
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakeo Miki
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device including a DLL circuit, a control logic includes a mode register, a command decoder, and a control signal generating unit outputting an output control signal of the DLL circuit. The control signal generating unit selects one of an ACT command and a READ command as a trigger for starting output of a clock, in accordance with a /CAS latency. When the /CAS latency is larger than a certain value, the READ command is used as the trigger. Output of the DLL clock can be stopped for a period from the input of the ACT command until the input of the READ command, so that power consumption can be reduced.
Claims16
A semiconductor memory device, comprising:
- a memory array including memory cells arranged in a matrix of rows and columns;
- a first output circuit outputting a first output signal to outside the semiconductor memory device in synchronization with a first clock signal, in response to data reading from said memory array;
- a DLL circuit receiving and delaying an external clock signal and generating said first clock signal;
- and
- a control circuit making said DLL circuit activate said first clock signal in accordance with a control signal from outside the semiconductor memory device;
- wherein said control circuit includes a command decode circuit decoding said control signal and detecting a plurality of commands, and
- said control circuit makes said DLL circuit activate said first clock signal in accordance with a first command of said plurality of commands, and makes said DLL circuit inactivate said first clock signal in accordance with a second command of said plurality of commands.
4 more elements
A semiconductor memory device, comprising:
- a memory array including memory cells arranged in a matrix of rows and columns;
- a first output circuit outputting a first output signal to outside the semiconductor memory device in synchronization with a first clock signal, in response to data reading from said memory array;
- a DLL circuit receiving and delaying an external clock signal and generating said first clock signal;
- and
- a control circuit making said DLL circuit activate said first clock signal in accordance with a control signal from outside the semiconductor memory device;
- wherein said DLL circuit includes
- a delay line receiving said external clock signal and delaying the received signal for delay time according to a delay control signal,
- a phase detector detecting a phase difference between an output of said delay line and said external clock signal,
- a delay control circuit outputting said delay control signal in accordance with an output of said phase detector, and
- a first clock driving circuit activated in response to a first enable signal, to receive an output of said delay line and to output said first clock signal.
7 more elements
A semiconductor memory device, comprising:
- a memory array including memory cells arranged in a matrix of rows and columns;
- a first output circuit outputting a first output signal to outside the semiconductor memory device in synchronization with a first clock signal, in response to data reading from said memory array;
- a DLL circuit receiving and delaying an external clock signal and generating said first clock signal;
- and
- a control circuit making said DLL circuit activate said first clock signal in accordance with a control signal from outside the semiconductor memory device;
- wherein said control circuit includes a command decode circuit decoding said control signal and detecting a plurality of commands, and
- said control circuit makes said DLL circuit activate said first clock signal in accordance with a first command of said plurality of commands, and makes said DLL circuit inactivate said first clock signal after a predetermined period needed for an operation according to said first command to be completed.
4 more elements
A semiconductor memory device, comprising:
- a memory array including memory cells arranged in a matrix of rows and columns;
- a first output circuit outputting a first output signal to outside the semiconductor memory device in synchronization with a first clock signal, in response to data reading from said memory array;
- a DLL circuit receiving and delaying an external clock signal and generating said first clock signal;
- and
- a control circuit making said DLL circuit activate said first clock signal in accordance with a control signal from outside the semiconductor memory device;
- wherein said control signal includes an enable signal of said external clock signal, and
- said control circuit makes said DLL circuit inactivate said first clock signal when said enable signal is inactivated for at least a predetermined period.
4 more elements
A semiconductor memory device, comprising:
- a memory array including memory cells arranged in a matrix of rows and columns;
- a first output circuit outputting a first output signal to outside the semiconductor memory device in synchronization with a first clock signal, in response to data reading from said memory array;
- a DLL circuit receiving and delaying an external clock signal and generating said first clock signal;
- and
- a control circuit making said DLL circuit activate said first clock signal in accordance with a control signal from outside the semiconductor memory device;
- wherein said first output signal is a data strobe signal corresponding to read data read from said memory array.
3 more elements
A semiconductor memory device, comprising:
- a memory array including memory cells arranged in a matrix of rows and columns;
- a first output circuit outputting a first output signal to outside the semiconductor memory device in synchronization with a first clock signal, in response to data reading from said memory array;
- a DLL circuit receiving and delaying an external clock signal and generating said first clock signal;
- and
- a control circuit making said DLL circuit activate said first clock signal in accordance with a control signal from outside the semiconductor memory device;
- and
- a second output circuit outputting, in synchronization with a second clock signal, a strobe signal corresponding to read data read from said memory array,
- said DLL circuit activating said first clock signal after starting activation of said second clock signal.
5 more elements
A semiconductor memory device, comprising:
- a memory array including memory cells arranged in a matrix of rows and columns;
- a data output circuit receiving read data from said memory array and outputting the read data to outside the semiconductor memory device in synchronization with an internal clock signal;
- and
- a DLL circuit receiving and delaying an external clock signal to generate said internal clock signal,
- said DLL circuit including
- a delay line receiving said external clock signal and delaying the received signal for delay time according to a delay control signal,
- a phase detector detecting a phase difference between an output of said delay line and said external clock signal,
- a delay control circuit outputting said delay control signal in accordance with an output of said phase detector, and
- a clock driving circuit activated in accordance with the output of said phase detector, to receive an output of said delay line and to output said internal clock signal.
6 more elements
Dependencies are inferred from the claim text.