Semiconductor integrated circuit device

A semiconductor integrated circuit device comprising:

• a first latch circuit which has a first input terminal for receiving a first input signal and a first output terminal, and operates in response to a first operation timing signal;
• a second latch circuit which has a second input terminal for receiving a second input signal and a second output terminal, and operates in response to a second operation timing signal;
• a third latch circuit which has a third input terminal and a third output terminal, and operates in response to a third operation timing signal;
• a first selection circuit which has a fourth input terminal for receiving a first output signal from said first output terminal, a fifth input terminal, and a fourth output terminal;
• a second selection circuit which has a sixth input terminal for receiving a second output signal from the second output terminal of said second latch circuit, a seventh input terminal, and a fifth output terminal;
• a first switch for transmitting said first input signal to said third input terminal and transmitting a third output signal of said third latch circuit to said fifth input terminal in a first state;
• and
• a second switch for transmitting said second input signal to said third input terminal and transmitting the third output signal of said third latch circuit to said seventh input terminal in a second state,
• wherein said first selection circuit performs a first operation of transmitting a signal corresponding to said third output signal to said fourth output terminal in said first state, and a second operation of transmitting the first output signal in place of said fourth output signal to said third output terminal when said third and first output signals are different from each other,
• wherein said first selection circuit performs a third operation of transmitting said first output signal to said fourth output terminal in said second state,
• wherein said first operation timing signal in said first state is generated behind said third operation timing signal,
• wherein said first latch circuit is limited to an operation period shorter than an operation period of said first timing signal in accordance with an operation frequency or a detection signal of coincidence of said first and third output signals in said first operation,
• wherein said second selection circuit performs a fourth operation of transmitting a signal corresponding to said third output signal to said fifth output terminal in said second state, and a fifth operation of transmitting said second output signal in place of said third output signal to said fifth output terminal when said third and second output signals are different from each other,
• wherein said second selection circuit performs a sixth operation of transmitting said second output signal to said fifth output terminal in said first state in said first operation mode,
• wherein said second operation timing signal in said second state is generated behind said third operation timing signal, and
• wherein said second latch circuit is limited to an operation period shorter than an operation period by said second timing signal in accordance with the operation frequency or a detection signal of coincidence between said third and second output signals in said fourth operation.

A semiconductor integrated circuit device comprising:

• a first latch circuit which has a first input terminal for receiving a first input signal and a first output terminal, and operates in response to a first operation timing signal;
• a second latch circuit which has a second input terminal for receiving said input signal and a second output terminal, and operates in response to a second operation timing signal;
• a third latch circuit which has a third input terminal and a third output terminal, and operates in response to a third operation timing signal;
• a first selection circuit which has a fourth input terminal for receiving a first output signal from said first output terminal of said first latch circuit, a fifth input terminal, and a fourth output terminal;
• a second selection circuit having a sixth input terminal for receiving a second output signal from the second output terminal of said second latch circuit, a seventh input terminal, and a fifth output terminal;
• a first switch for transmitting said first input signal to said third input terminal and transmitting the third output signal of said third latch circuit to said fifth input terminal in a first state in a first operation mode;
• and
• a second switch for transmitting said second input signal to said third input terminal and transmitting the third output signal of said third latch circuit to said seventh input terminal in a second state in the first operation mode,
• wherein said first selection circuit performs a first operation of transmitting a signal corresponding to said third output signal to said third output terminal in a first state in said first operation mode, and a second operation of transmitting the first output signal in place of said third output signal to said third output terminal when said third and first output signals are different from each other,
• wherein said first selection circuit performs a third operation of transmitting said first output signal to said third output terminal in a second state in said first operation mode,
• wherein said first operation timing signal in said first state in said first operation mode is generated behind said third operation timing signal, wherein said first latch circuit is limited to an operation period shorter than an operation period of said first timing signal in accordance with an operation frequency or a detection signal of coincidence of said first and third output signals in said first operation,
• wherein said second selection circuit performs a fourth operation of transmitting a signal corresponding to said third output signal to said fourth output terminal in said second state in said first operation mode, and a fifth operation of transmitting said second output signal in place of said third output signal to said fourth output terminal when said third and second output signals are different from each other,
• wherein said second selection circuit performs a sixth operation of transmitting said second output signal to said fourth output terminal in said first state in said first operation mode,
• wherein said second operation timing signal in said second state in said first operation mode is generated behind said third operation timing signal,
• wherein said second latch circuit is limited to an operation period shorter than an operation period by said second timing signal in accordance with the operation frequency or a detection signal of coincidence between said third and second output signals in said fourth operation, and
• wherein either said first or second switch is set to said connection state in a second operation mode, said first and second operation timings are set behind those in said first operation mode, and first and second output signals corresponding to first and second input signals are outputted in parallel through said first and second selection circuits.

A semiconductor integrated circuit device comprising:

• a first amplification circuit which receives an input signal from a first input terminal;
• a second amplification circuit which receives an input signal from a second input terminal;
• and
• a selection circuit which outputs one of a first output signal of said first amplification circuit and a second output signal of said second amplification circuit, wherein an operation start timing of said second amplification circuit is set behind an operation start timing of said first amplification circuit,
• wherein said selection circuit receives said first output signal and then said second output signal,
• wherein, when said second output signal is different from said first output signal, said selection circuit switches an output of said first output signal to an output of said second output signal so that said second output signal can be outputted, and
• wherein said second amplification circuit is controlled so that an operation period of said second amplification circuit becomes shorter than an operation period of said first amplification circuit.