High speed signal path and method

A high speed propagation circuit, comprising:

• a control circuit structured to alternately generate first and second values of a control signal;
• a first high speed data path having a plurality of inverters coupled in series with each other between a first input node and a first output node, a plurality of the inverters being skewed toward a first polarity and alternating with a plurality of the inverters skewed toward a second polarity that is different from the first polarity, the first high speed data path further comprising a logic circuit operative to couple an input signal terminal to the first input node responsive to the first value of the control signal, the first high speed data path further comprising a first preset circuit operative to preset an input to one of the inverters to a logic level corresponding to a voltage from which the inverter is skewed to accelerate a transition, the input being preset responsive to the second value of the control signal;
• and
• a second high speed data path having a plurality of inverters coupled in series with each other between a second input node and a second output node, a plurality of the inverters being skewed toward the first polarity and alternating with a plurality of the inverters skewed toward the second polarity, the second high speed data path further comprising a second logic circuit operative to couple an output of a pulse generator to the second input node responsive to the first value of the control signal, the second high speed data path further comprising a second preset circuit operative to preset an input to one of the inverters to a logic level corresponding to a voltage from which the inverter is skewed to accelerate a transition, the input being preset responsive to the second value of the control signal, the inverters in the second high speed data path collectively being skewed so that a signal applied to the input signal terminal of the first high speed data path is coupled to the first output node of the first high speed data path for a period that encompasses a period that a signal applied to the second input signal terminal of the second high speed data path is coupled to the second output node of the second high speed data path.

A high speed propagation circuit, comprising:

• a first series of alternately skewed inverters coupled between a signal input node and a signal output terminal;
• a second series of alternately skewed inverters coupled between a clock input node and a clock output terminal, the inverters in the second series being skewed in a manner causing a signal coupled to the first series of inverters to be present at the signal output terminal before and after a clock signal coupled to the second series of inverters is present at the clock output terminal;
• and
• a preset circuit operative to preset the inverters in the first and second series to a logic level from which a transition will be accelerated.

A synchronous memory device, comprising:

• an address bus adapted to receive address signals;
• a control bus adapted to receive control signals, including a clock signal;
• a data bus adapted to receive and output data signals;
• at least one a memory-cell array;
• an address decoder coupled between the address bus and the memory-cell array;
• a data path coupled between the memory-cell array and the data bus;
• a control circuit coupled the control bus, the memory-cell array, the address decoder and the data path, the control circuit being operable to generate control signals to control the operation of the memory device in synchronism with the clock signal;
• and
• a high speed signal path included in the memory device, the high speed signal path comprising:
• a first set of inverters, each of the inverters in the first set being skewed toward a first polarity of signal transition so that each of the inverters in the first set accelerates a transition from a first logic level to a second logic level;
• a second set of inverters, each of the inverters in the second set being skewed toward a second polarity of signal transition, the second polarity being different from the first polarity so that each of the inverters in the second set accelerates a transition from the second logic level to the first logic level, the inverters in the first and second set being coupled in series with each other between an input node and an output node with the inverters in the first set alternating with the inverters in the second set;
• and
• a logic circuit coupling an input terminal to the input node, the logic circuit being operative to couple the input terminal to the input node responsive to a first control signal having a first value, and being operable to couple an input of one of the inverters to a reference voltage responsive to a second control signal having a first value, the first and second control signals being complements of each other, the first value of the second control signal being present when the first control signal has other than the first value, the reference voltage being a voltage corresponding the logic level from which the inverter accelerates a transition, the logic circuit including a logic gate having a first input terminal coupled to the input terminal, a second input coupled to receive the first or second control signal, and an output terminal coupled to the input node.

A synchronous memory device, comprising:

• an address bus adapted to receive address signals;
• a control bus adapted to receive control signals, including an external clock signal;
• a data bus adapted to receive and output data signals;
• at least one a memory-cell array;
• an address decoder coupled between the address bus and the memory-cell array;
• a data path coupled between the memory-cell array and the data bus;
• a control circuit coupled the control bus, the memory-cell array, the address decoder and the data path, the control circuit being operable to generate control signals to control the operation of the memory device in synchronism with the clock signal;
• and
• a high speed signal path included in the memory device, the high speed signal path comprising:
• a first series of alternately skewed inverters coupled between a signal input node and a signal output terminal;
• a second series of alternately skewed inverters coupled between a clock input node and a clock output terminal, the inverters in the second series being skewed in a manner causing a signal coupled to the first series of inverters to be present at the signal output terminal before and after an internal clock signal derived from the external clock signal and coupled to the second series of inverters is present at the clock output terminal;
• and
• a preset circuit operative to preset the inverters in the first and second series to a logic level from which a transition will be accelerated.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a synchronous memory device, comprising:
• an address bus adapted to receive address signals;
• a control bus adapted to receive control signals, including a clock signal;
• a data bus adapted to receive and output data signals;
• at least one a memory-cell array;
• an address decoder coupled between the address bus and the memory-cell array;
• a data path coupled between the memory-cell array and the data bus;
• a control circuit coupled the control bus, the memory-cell array, the address decoder and the data path, the control circuit being operable to generate control signals to control the operation of the memory device in synchronism with the clock signal;
• and
• a high speed signal path included in the memory device, the high speed signal path comprising:
• a first set of inverters, each of the inverters in the first set being skewed toward a first polarity of signal transition so that each of the inverters in the first set accelerates a transition from a first logic level to a second logic level;
• a second set of inverters, each of the inverters in the second set being skewed toward a second polarity of signal transition, the second polarity being different from the first polarity so that each of the inverters in the second set accelerates a transition from the second logic level to the first logic level, the inverters in the first and second set being coupled in series with each other between an input node and an output node with the inverters in the first set alternating with the inverters in the second set;
• and
• a logic circuit coupling an input terminal to the input node, the logic circuit being operative to couple the input terminal to the input node responsive to a first control signal having a first value, and being operable to couple an input of one of the inverters to a reference voltage responsive to a second control signal having a first value, the first and second control signals being complements of each other, the first value of the second control signal being present when the first control signal has other than the first value, the reference voltage being a voltage corresponding the logic level from which the inverter accelerates a transition, the logic circuit including a logic gate having a first input terminal coupled to the input terminal, a second input coupled to receive the first or second control signal, and an output terminal coupled to the input node.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a synchronous memory device, comprising:
• an address bus adapted to receive address signals;
• a control bus adapted to receive control signals, including an external clock signal;
• a data bus adapted to receive and output data signals;
• at least one a memory-cell array;
• an address decoder coupled between the address bus and the memory-cell array;
• a data path coupled between the memory-cell array and the data bus;
• a control circuit coupled the control bus, the memory-cell array, the address decoder and the data path, the control circuit being operable to generate control signals to control the operation of the memory device in synchronism with the clock signal;
• and
• a high speed signal path included in the memory device, the high speed signal path comprising:
• a first series of alternately skewed inverters coupled between a signal input node and a signal output terminal;
• a second series of alternately skewed inverters coupled between a clock input node and a clock output terminal, the inverters in the second series being skewed in a manner causing a signal coupled to the first series of inverters to be present at the signal output terminal before and after an internal clock signal derived from the external clock signal and coupled to the second series of inverters is present at the clock output terminal;
• and
• a preset circuit operative to preset the inverters in the first and second series to a logic level from which a transition will be accelerated.

A method of designating the validity of a digital signal, comprising:

• coupling the digital signal through a first series of inverters in a manner that accelerates a first transition of the digital signal and delays a second transition of the digital signal;
• coupling a clock signal through a second series of inverters in a manner that accelerates a first transition of the clock signal and delays a second transition of the clock signal, the transitions of the clock signal being delayed and accelerated to a lesser degree than the transitions of the digital signal are accelerated and delayed, respectively;
• and
• designating the digital signal at the output of the first series of inverters as being valid when the clock signal is being output from the second series of inverters.

A high speed signal path, comprising:

• a first set of inverters, each of the inverters in the first set being skewed toward a first polarity of signal transition so that each of the inverters in the first set accelerates a transition from a first logic level to a second logic level;
• a second set of inverters, each of the inverters in the second set being skewed toward a second polarity of signal transition, the second polarity being different from the first polarity so that each of the inverters in the second set accelerates a transition from the second logic level to the first logic level, the inverters in the first and second set being coupled in series with each other between an input node and an output node with the inverters in the first set alternating with the inverters in the second set;
• and
• a logic circuit coupling an input terminal to the input node, the logic circuit being operative to couple the input terminal to the input node responsive to a first control signal having a first value, and being operable to couple an input of one of the inverters to a reference voltage responsive to a second control signal having a first value, the first value of the second control signal being present when the first control signal has other than the first value, the reference voltage being a voltage corresponding the logic level from which the inverter accelerates a transition;
• and
• a pulse generator structured to generate the second control signal, the pulse generator being operative to generate the first value of the second control signal whenever the pulse generator is not generating a second value of the second control signal, the second value of the second control signal being generated responsive to a predetermined edge of a clock signal, the second value of the second control signal being generated for a duration that is substantially shorter than half of the period of the clock signal.

A high speed signal path, comprising:

• a first set of inverters, each of the inverters in the first set being skewed toward a first polarity of signal transition so that each of the inverters in the first set accelerates a transition from a first logic level to a second logic level;
• a second set of inverters, each of the inverters in the second set being skewed toward a second polarity of signal transition, the second polarity being different from the first polarity so that each of the inverters in the second set accelerates a transition from the second logic level to the first logic level, the inverters in the first and second set being coupled in series with each other between an input node and an output node with the inverters in the first set alternating with the inverters in the second set;
• and
• a logic circuit coupling an input terminal to the input node, the logic circuit being operative to couple the input terminal to the input node responsive to a first control signal having a first value, and being operable to couple an input of one of the inverters to a reference voltage responsive to a second control signal having a first value, the first and second control signals being complements of each other, the first value of the second control signal being present when the first control signal has other than the first value, the reference voltage being a voltage corresponding the logic level from which the inverter accelerates a transition, the logic circuit including a logic gate having a first input terminal coupled to the input terminal, a second input coupled to receive the first or second control signal, and an output terminal coupled to the input node.