Column multiplexer for semiconductor memories
AssigneeSTMicroelectronics S.r.l.
InventorLuigi Pascucci
Life of this patent
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Abstract
The column multiplexer is for a memory matrix having memory cells arranged in rows and columns. The multiplexer includes input lines for input signals, a plurality of output lines for electrical connection to the columns of the matrix, a selective connection device for selecting, in a first operation mode, at least one output line of the plurality of output lines in such a way as to connect it selectively to the input lines. In the first operation mode, the selective connection device selects a first group of output lines among the plurality of output lines, including at least three first lines.
Claims39
A column multiplexer for a memory matrix comprising memory cells arranged in rows and columns, the column multiplexer comprising:
- input lines for input signals;
- a plurality of output lines for electrical connection to the columns of the matrix;
- and
- selective connection means for selecting, in a first operation mode, a first group of output lines from among said plurality of output lines to selectively connect the first group of output lines to the input lines, the first group of output lines comprising at least three first output lines.
A column multiplexer for a memory matrix comprising memory cells arranged in rows and columns, the column multiplexer comprising:
- input lines for input signals;
- a plurality of output lines for connection to the columns of the matrix;
- and
- a selective connection unit to select a first group of output lines from the plurality of output lines to selectively connect the first group of output lines to the input lines, the first group of output lines comprising at least three first output lines.
A column selection system for a memory matrix comprising memory cells arranged in rows and columns, said system comprising:
- a column decoder having a plurality of inputs for corresponding column address signals and a plurality of outputs to supply control signals obtained from decoding the address signals;
- and
- a column multiplexer for selecting at least one column of said matrix and comprising a plurality of control lines to receive the control signals, said multiplexer further including
- input lines for input signals,
- a plurality of output lines for connection to the columns of the matrix, and
- a selective connection unit to select a first group of output lines from the plurality of output lines to selectively connect the first group of
- output lines to the input lines, the first group of output lines comprising at least three first output lines.
A circuit integrated into a semiconductor structure comprising:
- a memory matrix comprising memory cells arranged in rows and columns;
- and
- a column multiplexer for the memory matrix and comprising
- input lines for input signals,
- a plurality of output lines for connection to the columns of the matrix, and
- a selective connection unit to select a first group of output lines from the plurality of output lines to selectively connect the first group of output lines to the input lines, the first group of output lines comprising at least three first output lines.
Dependencies are inferred from the claim text.