Nonvolatile semiconductor memory device having changeable spare memory address
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-Hee Cho, Yeong-Taek Lee
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Abstract
A nonvolatile semiconductor memory device comprising a main memory cell array and a spare memory cell array, capable of freely accessing data in the spare memory cell array irrespective of the physical addresses of the spare memory cell array, and a method thereof are disclosed. The logical addresses of the spare memory cell array are assigned prior to the logical addresses of the main memory cell array in response to a first control signal, and data stored in the spare memory cell array is read earlier than data in the main memory cell array.
Claims20
A method of reading data in a nonvolatile semiconductor memory device comprising a spare memory cell array and a main memory cell array comprising a plurality NAND cell strings, wherein physical addresses of the main memory cell array are placed prior to physical addresses of the spare memory cell array, the method comprising the steps of:
- assigning logical addresses of the spare memory cell array prior to logical addresses of the main memory cell array in response to a first control signal;
- and
- reading data stored in the spare memory cell array earlier than data in the main memory cell array using the logical addresses.
A nonvolatile semiconductor memory device, comprising:
- a memory cell array comprising a main memory cell array and a spare memory cell array comprising a plurality NAND cell strings, wherein physical addresses of the main memory cell array are placed prior to physical addresses of the spare memory cell array;
- a column selector for selecting column path of the memory cell array;
- a column decoder for applying a column decoding signal to the column selector;
- an address counter for counting external addresses to output a column address counting signal to the column decoder, wherein the address counter counts logical addresses of the spare memory cell array prior to logical addresses of the main memory cell array in response to a spare start read signal at a spare start whole page sequential read mode, and wherein the address counter counts the logical addresses of the main memory cell array prior to the logical addresses of the spare memory cell array at a main start whole page sequential read mode;
- a final point moving circuit for receiving the spare start read signal and a spare enable signal to generate a final point signal;
- a final column address detector for detecting a final column address in response to the final point signal to enter into a next spare start whole page sequential read mode and outputting the detected address as a page end signal;
- a spare to main controller for generating a spare to main signal in response to the spare start read signal;
- and
- a reset controller for resetting the address counter in response to the page end signal and the spare to main signal to count the addresses of the memory cell array from zero (0) logical address.
A method of reading data in a nonvolatile semiconductor memory device comprising a spare memory cell array and a main memory cell array, comprising the step of:
- performing one of a main data only sequential read mode, a spare data only sequential read mode, and a main start whole page sequential read mode, in response to at least a first control signal that indicates data is to be read in the main memory cell array earlier than in the spare memory cell array;
- and
- performing a spare start whole page sequential read mode in response to at least a second control signal that indicates data is to be read in the spare memory cell array earlier than in the main memory cell array by assigning logical addresses of the spare memory cell array prior to logical addresses of the main memory cell array.
A method for reading data in a nonvolatile semiconductor memory device comprising a spare memory cell array and a main memory cell array comprising a plurality of NAND cell strings, the method comprising the steps of:
- receiving a first control signal that indicates data is to be read in the spare memory cell array earlier than in the main memory cell array;
- counting addresses of the spare memory cell array and reading data at the counted addresses of the spare memory cell array;
- and
- counting addresses of the main memory cell array and reading data at the counted addresses of the main memory cell array after counting each address of the spare memory cell array.
Dependencies are inferred from the claim text.